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PDF M28W320ECB Data sheet ( Hoja de datos )
| Número de pieza | M28W320ECB | |
| Descripción | 32 Mbit 3V Supply Flash Memory | |
| Fabricantes | STMicroelectronics | |
| Logotipo |  |
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M28W320ECT
M28W320ECB
32 Mbit (2Mb x16, Boot Block)
3V Supply Flash Memory
FEATURES SUMMARY
s SUPPLY VOLTAGE
– VDD = 2.7V to 3.6V Core Power Supply
– VDDQ= 1.65V to 3.6V for Input/Output
– VPP = 12V for fast Program (optional)
s ACCESS TIME: 70, 85, 90,100ns
s PROGRAMMING TIME:
– 10µs typical
– Double Word Programming Option
– Quadruple Word Programming Option
s COMMON FLASH INTERFACE
s MEMORY BLOCKS
– Parameter Blocks (Top or Bottom location)
– Main Blocks
s BLOCK LOCKING
– All blocks locked at Power Up
– Any combination of blocks can be locked
– WP for Block Lock-Down
s SECURITY
– 128 bit user Programmable OTP cells
– 64 bit unique device identifier
s AUTOMATIC STAND-BY MODE
s PROGRAM and ERASE SUSPEND
s 100,000 PROGRAM/ERASE CYCLES per
BLOCK
s ELECTRONIC SIGNATURE
– Manufacturer Code: 20h
– Top Device Code, M28W320ECT: 88BAh
– Bottom Device Code, M28W320ECB: 88BBh
Figure 1. Packages
FBGA
TFBGA47 (ZB)
6.39 x 6.37mm
TSOP48 (N)
12 x 20mm
February 2003
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1 page  
M28W320ECT, M28W320ECB
SUMMARY DESCRIPTION
The M28W320EC is a 32 Mbit (2 Mbit x 16) non-
volatile Flash memory that can be erased electri-
cally at the block level and programmed in-system
on a Word-by-Word basis. These operations can
be performed using a single low voltage (2.7 to
3.6V) supply. VDDQ allows to drive the I/O pin
down to 1.65V. An optional 12V VPP power supply
is provided to speed up customer programming.
The device features an asymmetrical blocked ar-
chitecture. The M28W320EC has an array of 71
blocks: 8 Parameter Blocks of 4 KWord and 63
Main Blocks of 32 KWord. M28W320ECT has the
Parameter Blocks at the top of the memory ad-
dress space while the M28W320ECB locates the
Parameter Blocks starting from the bottom. The
memory maps are shown in Figure 5, Block Ad-
dresses.
The M28W320EC features an instant, individual
block locking scheme that allows any block to be
locked or unlocked with no latency, enabling in-
stant code and data protection. All blocks have
three levels of protection. They can be locked and
locked-down individually preventing any acciden-
tal programming or erasure. There is an additional
hardware protection against program and erase.
When VPP ≤ VPPLK all blocks are protected against
program or erase. All blocks are locked at Power
Up.
Each block can be erased separately. Erase can
be suspended in order to perform either read or
program in any other block and then resumed.
Program can be suspended to read data in any
other block and then resumed. Each block can be
programmed and erased over 100,000 cycles.
The device includes a Protection Register to in-
crease the protection of a system design. The Pro-
tection Register is divided into two segments, the
first is a 64 bit area which contains a unique device
number written by ST, while the second is a 128 bit
area, one-time-programmable by the user. The
user programmable segment can be permanently
protected. Figure 6, shows the Protection Register
Memory Map.
Program and Erase commands are written to the
Command Interface of the memory. An on-chip
Program/Erase Controller takes care of the tim-
ings necessary for program and erase operations.
The end of a program or erase operation can be
detected and any error conditions identified. The
command set required to control the memory is
consistent with JEDEC standards.
The memory is offered in TSOP48 (10 X 20mm)
and TFBGA47 (6.39 x 6.37mm, 0.75mm pitch)
packages and is supplied with all the bits erased
(set to ’1’).
Figure 2. Logic Diagram
VDD VDDQ VPP
21
A0-A20
W
E
G
RP
WP
16
DQ0-DQ15
M28W320ECT
M28W320ECB
VSS
AI05517
Table 1. Signal Names
A0-A20
Address Inputs
DQ0-DQ15 Data Input/Output
E Chip Enable
G Output Enable
W Write Enable
RP Reset
WP Write Protect
VDD Core Power Supply
VDDQ
Power Supply for
Input/Output
VPP
Optional Supply Voltage for
Fast Program & Erase
VSS Ground
NC Not Connected Internally
5/52
5 Page 
M28W320ECT, M28W320ECB
COMMAND INTERFACE
All Bus Write operations to the memory are inter-
preted by the Command Interface. Commands
consist of one or more sequential Bus Write oper-
ations. An internal Program/Erase Controller han-
dles all timings and verifies the correct execution
of the Program and Erase commands. The Pro-
gram/Erase Controller provides a Status Register
whose output may be read at any time during, to
monitor the progress of the operation, or the Pro-
gram/Erase states. See Table 3, Command
Codes, for a summary of the commands and see
Appendix 22, Table 32, Write State Machine Cur-
rent/Next, for a summary of the Command Inter-
face.
The Command Interface is reset to Read mode
when power is first applied, when exiting from Re-
set or whenever VDD is lower than VLKO. Com-
mand sequences must be followed exactly. Any
invalid combination of commands will reset the de-
vice to Read mode. Refer to Table 4, Commands,
in conjunction with the text descriptions below.
Read Memory Array Command
The Read command returns the memory to its
Read mode. One Bus Write cycle is required to is-
sue the Read Memory Array command and return
the memory to Read mode. Subsequent read op-
erations will read the addressed location and out-
put the data. When a device Reset occurs, the
memory defaults to Read mode.
Read Status Register Command
The Status Register indicates when a program or
erase operation is complete and the success or
failure of the operation itself. Issue a Read Status
Register command to read the Status Register’s
contents. Subsequent Bus Read operations read
the Status Register at any address, until another
command is issued. See Table 11, Status Register
Bits, for details on the definitions of the bits.
The Read Status Register command may be is-
sued at any time, even during a Program/Erase
operation. Any Read attempt during a Program/
Erase operation will automatically output the con-
tent of the Status Register.
Read Electronic Signature Command
The Read Electronic Signature command reads
the Manufacturer and Device Codes and the Block
Locking Status, or the Protection Register.
The Read Electronic Signature command consists
of one write cycle, a subsequent read will output
the Manufacturer Code, the Device Code, the
Block Lock and Lock-Down Status, or the Protec-
tion and Lock Register. See Tables 5, 6 and 7 for
the valid address.
Table 3. Command Codes
Hex Code
Command
01h Block Lock confirm
10h Program
20h Erase
2Fh Block Lock-Down confirm
30h Double Word Program
40h Program
50h Clear Status Register
55h Reserved
56h Quadruple Word Program
60h
Block Lock, Block Unlock, Block Lock-
Down
70h Read Status Register
90h Read Electronic Signature
98h Read CFI Query
B0h Program/Erase Suspend
C0h Protection Register Program
D0h
Program/Erase Resume, Block Unlock
confirm
FFh Read Memory Array
Read CFI Query Command
The Read Query Command is used to read data
from the Common Flash Interface (CFI) Memory
Area, allowing programming equipment or appli-
cations to automatically match their interface to
the characteristics of the device. One Bus Write
cycle is required to issue the Read Query Com-
mand. Once the command is issued subsequent
Bus Read operations read from the Common
Flash Interface Memory Area. See Appendix B,
Common Flash Interface, Tables 26, 27, 28, 29,
30 and 31 for details on the information contained
in the Common Flash Interface memory area.
Block Erase Command
The Block Erase command can be used to erase
a block. It sets all the bits within the selected block
to ’1’. All previous data in the block is lost. If the
block is protected then the Erase operation will
abort, the data in the block will not be changed and
the Status Register will output the error.
Two Bus Write cycles are required to issue the
command.
s The first bus cycle sets up the Erase command.
11/52
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