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PDF TDA8007BHL Data sheet ( Hoja de datos )
| Número de pieza | TDA8007BHL | |
| Descripción | Multiprotocol IC card interface | |
| Fabricantes | NXP Semiconductors | |
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TDA8007BHL
Multiprotocol IC card interface
Rev. 9.1 — 18 June 2012
Product data sheet
1. General description
The TDA8007BHL is a cost-effective card interface for dual smart card readers.
Controlled through a parallel bus, it meets all requirements of ISO 7816, GSM 11-11,
EMV4.2 and EMV 2000. It is addressed on a non-multiplexed 8-bit databus, by means of
address registers AD0, AD1, AD2 and AD3. TDA8007BHL/C3 can be also addressed
through a multiplexed access. The integrated ISO UART and the time-out counters allow
easy use even at high baud rates with no real time constraints. Due to its chip select,
external input/output and interrupt features, it greatly simplifies the realization of a reader
of any number of cards. It gives the cards and the reader a very high level of security, due
to its special hardware against ESD, short-circuiting, power failure, etc. The integrated
step-up converter allows operation within a supply voltage range of 2.7 V to 6 V.
TDA8007BHL/C4 supports only non multiplex access and TDA8007BHL/C3 support both
non multiplexed and multiplexed access.
2. Features and benefits
Control and communication through an 8-bit parallel interface, compatible with
non-multiplexed memory access, TDA8007BHL/C3 can be also addressed through a
multiplexed memory access
Specific ISO UART with parallel access input/output for automatic convention
processing, variable baud rate through frequency or division ratio programming, error
management at character level for T = 0 and extra guard time register
FIFO for 1 to 8 characters in reception mode
Parity error counter in reception mode and in transmission mode with automatic
re-transmission
Dual VCC generation: 5 V ± 5 %, 65 mA (max.); 3 V ± 8 %, 50 mA (max.) or
1.8 V ± 10 %, 30 mA (max.); with controlled rise and fall times
Dual cards clock generation (up to 10 MHz), with three times synchronous frequency
doubling (fXTAL, 1⁄2fXTAL, 1⁄4fXTAL and 1⁄8fXTAL)
Cards clock stop (at high or low level) or 1.25 MHz (from internal oscillator) for cards
Power-down mode
Automatic activation and deactivation sequence through an independent sequencer
Supports the asynchronous protocols T = 0 and T = 1 in accordance with:
ISO 7816 and EMV4.2
Versatile 24-bit time-out counter for Answer To Reset (ATR) and waiting times
processing
Specific Elementary Time Unit (ETU) counter for Block Guard Time (BGT): 22 in T = 1
and 16 in T = 0
Minimum delay between two characters in reception mode:
1 page  
NXP Semiconductors
7. Pinning information
7.1 Pinning
TDA8007BHL
Multiprotocol IC card interface
RSTOUT 1
I/OAUX 2
I/O1 3
C81 4
PRES1 5
C41 6
CGND1 7
CLK1 8
VCC1 9
RST1 10
I/O2 11
C82 12
TDA8007BHL
36 RD
35 D7
34 D6
33 D5
32 D4
31 D3
30 D2
29 D1
28 D0
27 VDD
26 SAM
25 AGND
fce678
Fig 2. Pin configuration
7.2 Pin description
Table 3. Pin description
Symbol
Pin
RSTOUT
1
I/OAUX
2
I/O1 3
C81 4
PRES1
C41
5
6
CGND1
CLK1
VCC1
RST1
I/O2
7
8
9
10
11
Description
PMOS open-drain output for resetting external
devices
input or output for an I/O line from an auxiliary smart
card interface
input or output for the data line to/from card 1
(ISO C7 contact)
auxiliary I/O for ISO C8 contact (synchronous cards,
for instance) for card 1
card 1 presence contact input (active high)
auxiliary I/O for ISO C4 contact (synchronous cards,
for instance) for card 1
ground for card 1; must be connected to GND
clock output to card 1 (ISO C3 contact)
card 1 supply output voltage (ISO C1 contact)
card 1 reset output (ISO C2 contact)
input or output for the data line to/from card 2
(ISO C7 contact)
TDA8007BHL
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 9.1 — 18 June 2012
© NXP B.V. 2012. All rights reserved.
5 of 51
5 Page 
NXP Semiconductors
TDA8007BHL
Multiprotocol IC card interface
Cards 1, 2 and 3 have dedicated registers for setting the parameters of the ISO UART
(see Figure 9).
Programmable Divider Register (PDR)
Guard Time Register (GTR)
UART Configuration register 1 (UCR1)
UART Configuration Register 2 (UCR2)
Clock Configuration Register (CCR)
Cards 1 and 2 also have dedicated registers for controlling their power and clock
configuration. The Power Control Register (PCR) for card 3 is controlled externally.
Register PCR is also used for writing or reading on the auxiliary card contacts C4 and C8.
Card 1, 2 or 3 can be selected via the Card Select Register (CSR). When one card is
selected, the corresponding parameters are used by the ISO UART. Register CSR also
contains one bit for resetting the ISO UART (bit RIU = 0). This bit is reset after power-on
and must be set to logic 1 before starting with any one of the cards. It may be reset by
software when necessary.
When the specific parameters of the cards have been programmed, the UART may be
used with the following registers:
UART Receive Register (URR)
UART Transmit Register (UTR)
UART Status Register (USR)
Mixed Status Register (MSR).
In reception mode, a FIFO of 1 to 8 characters may be used and is configured with the
FIFO Control Register (FCR). This register is also used for the automatic re-transmission
of Not AcKnowledged (NAK) characters in transmission mode.
The Hardware Status Register (HSR) gives the status of the supply voltage, of the
hardware protections and of the card movements.
Registers HSR and USR give interrupts on pin INT when some of their bits have been
changed.
Register MSR does not give interrupts and may be used in the polling mode for some
operations; for this use, some of the interrupt sources within the registers USR and HSR
may be masked.
A 24-bit time-out counter may be started to give an interrupt after a number of ETU
programmed into the Time-Out Registers TOR1, TOR2 and TOR3. This will help the
microcontroller in processing different real-time tasks (ATR, WWT, BWT, etc.). This
counter is configured with a Time-Out counter Configuration (TOC) register. It may be
used as a 24-bit counter or as a 16-bit plus 8-bit counter. Each counter can be set to start
counting once data has been written, or on detection of a START bit on the I/O, or as
auto-reload.
TDA8007BHL
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 9.1 — 18 June 2012
© NXP B.V. 2012. All rights reserved.
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