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PDF EM78447S Data sheet ( Hoja de datos )
| Número de pieza | EM78447S | |
| Descripción | 8-Bit Microcontroller | |
| Fabricantes | ELAN Microelectronics | |
| Logotipo |  |
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EM78447S
8-Bit Microprocessor
with OTP ROM
Product
Specification
DOC. VERSION 1.2
ELAN MICROELECTRONICS CORP.
February 2010
1 page  
EM78447S
8-Bit Microcontroller with OTP ROM
1 General Description
EM78447S is an 8-bit microprocessor with low-power and high-speed CMOS
technology. The chip is integrated with on-chip watchdog timer (WDT), RAM, ROM,
real time clock/counter, external interrupt, power down mode, and tri-state I/O.
2 Features
Operating voltage range:
● 2.3V ~ 5.5V base on 0°C ~ 70°C
● 2.5V ~ 5.5V base on –20°C ~ 70°C
Operating frequency range (base on two
clocks):
● Crystal Mode:
DC ~ 20MHz @ 5V
DC ~ 8MHz @ 3V
DC ~ 4MHz @ 2.3V
● RC Mode:
DC ~ 4MHz @ 5V
DC ~ 4MHz @ 3V
DC ~ 4MHz @ 2.3V
Low power consumption:
● Less then 2.2 mA at 5V/4MHz
● Typically 30 µA at 3V/32KHz
● Typically 1 µA during sleep mode
4K × 13 bits on chip ROM
One configuration register to accommodate
user’s ID register requirements
148×8 bits on chip registers (SRAM, general
purpose register)
3 bi-directional I/O ports
5 level stacks for subroutine nesting
8-bit real time clock/counter (TCC) with
selective signal sources, trigger edges, and
overflow interrupt
Two clocks per instruction cycle
Power down (SLEEP) mode
Two available interruptions
• TCC overflow interrupt
• External interrupt
Programmable free running watchdog timer
10 programmable pull-high pins
2 programmable open-drain pins
2 programmable R-option pins
Package types:
• 28 pin DIP 600mil:
EM78447SAP
• 28 pin SOP(SOIC) 300mil: EM78447SAM
• 28 pin SSOP 209mil:
EM78447SAS
• 32 pin DIP 600mil:
EM78447SBP
• 32 pin SOP(SOIC) 450mil: EM78447SBWM
99.9% single instruction cycle commands
The transient point of system frequency
between HXT and LXT is around 400KHz
Product Specification (V1.2) 02.04.2010
(This specification is subject to change without further notice)
1
5 Page 
EM78447S
8-Bit Microcontroller with OTP ROM
Data Memory Configuration
00 R0
01 R1(TCC)
02 R2(PC)
03 R3(Status)
04 R4(RSR)
05 R5(Port5)
06 R6(Port6)
07 R7(Port7)
08 R8
09 R9
0A RA
0B RB
0C RC
0D RD
0E RE
0F RF
10
: 16x8
: Common
Register
1F
Stack
(5 level)
IOC5
IOC6
IOC7
IOCB
IOCE
IOCF
00 01 10 11
20
31x8
31x8
31x8
31x8
:
Bank
Bank
Bank
Bank
:
Register
Register
Register
Register
(Bank 0)
(Bank 1)
(Bank 2)
(Bank 3)
3E
3F R3F
Figure 4-3 Data Memory Configuration
Product Specification (V1.2) 02.04.2010
(This specification is subject to change without further notice)
7
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet EM78447S.PDF ] | |
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