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Número de pieza | NCT5655W | |
Descripción | 16-bit I2C-bus and SMBus GPIO controller | |
Fabricantes | novoTon | |
Logotipo | ||
Hay una vista previa y un enlace de descarga de NCT5655W (archivo pdf) en la parte inferior de esta página. Total 26 Páginas | ||
No Preview Available ! NCT5655Y/W
Nuvoton
NCT5655Y/W
16-bit I2C-bus and SMBus GPIO
controller with interrupt
Revision: 1.0 Date: May, 2016
-I-
Publication Release Date: May, 2016
Revision 1.0
1 page NCT5655Y/W
1. GENERAL DESCRIPTION
The NCT5655Y/W is a general purpose input/output IC with I2C-bus/SMBus that provides 16 bits of
General Purpose Input/Output (GPIO) expansion. The GPIO expanders provide a simple solution
when additional I/O is needed for push buttons, flashing LED output, BEEP functions, sensors and so
on. It also provides an interrupt to inform the system master when a transistion occurs on general
purpose input pins.
The NCT5655Y/W provides I2C-bus/SMBus address setting pins to set the address during power-on
reset or from external reset, allowing up to eight devices to share the same I2C-bus/SMBus.
2. FEATURES
2.1 General Features
Operating power supply voltage range of 2.3 V to 5.5 V
5 V tolerant I/Os
Polarity inversion register
General purpose output setting for level or pulse mode
Interrupt output setting for level or pulse mode
Interrupt notification support for system event occurs
Low standby current
Noise filter on SCL/SDA inputs
No glitch on power-up
Internal power-on reset
16 I/O pins which default to 16 inputs with push-pull or open-drain selection
Flashing LED output
PC beep output
0 Hz to 400 kHz clock frequency
Halogen free packages (RoHS Compliable) offered: QFN24 and TSSOP24
2.2 Key Specifications
Supply Voltage is 2.3 V to 5.5 V
Standby Current is 1uA max.
Operating Temperature is from -40 °C to 85 °C
-1-
Publication Release Date: May, 2016
Revision 1.0
5 Page NCT5655Y/W
6.2 I/O Port
data from
shift register
write pulse
data from
shift register
data from
shift register
write
configuration
pulse
write pulse
configuration
register
D SET Q
QCLR
D SET Q
QCLR
output type
register
D SET Q
QCLR
output port
register
read pulse
0
1
input port
register
D SET Q
QCLR
Q1
100 kΩ
Q2
output port
register data
VDD
I/O pin
VSS
input port
register
data from
shift register
write
polarity
pulse
polarity inversion
register
D SET Q
QCLR
to INT#
polarity
inversion
register data
When an I/O is configured as an input (default), FETs Q1 and Q2 are off, creating a high-impedance
input with a weak pull-up to VDD. The input voltage may be raised above VDD to a maximum of 5.5 V.
If the I/O is configured as an output, then either Q1 or Q2 is on, depending on the state of the Output
Port register. Care should be exercised if an external voltage is applied to an I/O configured as an
output because of the low-impedance path that exists between the pin and either VDD or VSS.
*GPIO Output Table:
GPIO CONFIGURATION
REGISTER
0
OUTPUT PORT
REGISTER
0
1
OUTPUT VALUE AT PIN
0
1
WAVE
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Publication Release Date: May, 2016
Revision 1.0
11 Page |
Páginas | Total 26 Páginas | |
PDF Descargar | [ Datasheet NCT5655W.PDF ] |
Número de pieza | Descripción | Fabricantes |
NCT5655W | 16-bit I2C-bus and SMBus GPIO controller | novoTon |
NCT5655Y | 16-bit I2C-bus and SMBus GPIO controller | novoTon |
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