PDF NCT5605Y Data sheet ( Hoja de datos )

Número de pieza	NCT5605Y
Descripción	SMBus GPIO Controller
Fabricantes	novoTon
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No Preview Available ! Nuvoton SMBus GPIO Controller NCT5605Y Revision: 1.0 Date: Nov, 2009 1 page NCT5605Y 1. GENERAL DESCRIPTION The NCT5605Y is a general purpose input/output IC with SMBusTM which provides 14 GPI/O pins. It also can provide SMBusTM address setting pins to set the address during power- on reset or from external reset. NCT5605Y SMBusTM Address is: 0 0 1 1 A2 A1 A0 R/W NCT5605Y also provides an interrupt to inform system that a transition occurs on general purpose input pins. By NCT5605Y, flashing LED output and beep function are also supported. 2. FEATURES 2.1 General Features  SMBusTM Compliance with 3.3V Voltage Levels  14pins Flexible GPIO Support  Interrupt Notification Support for System Event Occurs  Support General Purpose Output Setting for Level or Pulse Mode  Support Interrupt Output Setting for Level or Pulse mode  Support Internal Power-on Reset or External RST# Pin Reset.  Support Flashing LED Output  Support PC Beep Output  Chip Power down mode support  20-QFN Halogen free package (RoHS Compliable) 2.2 Key Specifications  Supply Voltage is 3.3V  Operating Supply Current is 150 uA typ.  Operating Temperature is from 0 °C to 70 °C -1- Publication Release Date: Nov, 2009 Revision 1.0 5 Page NCT5605Y 5.13 Register 12h – GP2 Polarity Inversion register BIT 7 6 5 4 3 2 1 0 R/W RW RW RW RW RW RW NA Default 000000 Refer to Section 6.2.1 for respective GPO2x pin type implementation. 5.14 Register 13h – GP2 input/output configuration register BIT 7 6 5 4 3 2 1 0 R/W RW RW RW RW RW RW NA Default 111111 This register configures the respective GPIO2x pin as input mode (“1”; by default) or output mode (“0”). 5.15 Register 14h – GP2 output style register BIT 7 6 5 4 3 2 1 0 R/W RW RW RW RW RW RW NA Default 000000 This register configures the respective GPO2x pins as level (“0”; by default) or pulse (“1”) output style. Set output port register (CR11) to “0” before switch the output style to pulse mode. 5.16 Register 15h – GP2 output mode register BIT 7 6 5 4 3 2 1 0 R/W RW RW RW RW RW RW NA Default 000000 This register configures the respective GPO2x output pads function as Open-drain (“0”; by default) or Push-pull (“1”) mode. 5.17 Register 16h – GP2 interrupt control register BIT 7 6 5 4 3 2 1 0 R/W RW RW RW RW RW RW NA Default 000000 This register configures the respective GPI2x pin interrupt control as disable (“0”; by default) or enable (“1”). *Clear interrupt status register (CR17) before set to enable. -7- Publication Release Date: Nov, 2009 Revision 1.0 11 Page

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