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PDF NCT3107S Data sheet ( Hoja de datos )
| Número de pieza | NCT3107S | |
| Descripción | DDR Termination Regulator | |
| Fabricantes | novoTon | |
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Nuvoton
DDR Termination Regulator
NCT3107S
DATE: NOVEMBER, 2011
Revision: A2
1 page  
NCT3107S
5. PIN DESCRIPTION
PIN NAME
GND
SD#
VSEN
VREF
VDDQ
AVIN
PVIN
VTT
EP
NO
1
2
3
4
5
6
7
8
PIN TYPE
Ground
I
AI
AO
AI
Power
AI
AO
DESCRIPTION
Ground
Shutdown VTT output voltage.
Feedback pin for regulating VTT.
Buffered internal reference voltage of ½VDDQ.
Input for internal reference equal to ½VDDQ.
Analog input pin for power source.
Analog input pin for internal power MOSFET source.
Output voltage for connection to termination resistors.
Exposed pad thermal connection. Connect to ground.
PIN TYPE
AO
AI
I
POWER
GROUND
PIN Attribute
Output pin (Analog)
Input pin (Analog)
Input pin (Digital)
Positive power supply input
Power supply ground
6. FUNCTIONAL DESCRIPTION
General Description
The NCT3107S is a sink/source linear regulator for DDR-SDRAM VTT bus termination. The
device contains a high speed operational amplifier to provide excellent response to load
transients and only requires a minimum output capacitance of 10uF. The NCT3107S also
incorporates a remote sensing function (VSEN pin) to provide superior load regulation and a
VREF output as a reference for the chipset and DIMMS. An additional feature found on the
NCT3107S is an active low shutdown (SD# pin) that provides Suspend to RAM (STR)
functionality. When SD# is pilled low, the VTT output voltage will be discharged to ground but,
VREF remains active. A power savings advantage can be obtained in this mode through lower
quiescent current.
Series Stub Termination Logic (SSTL) was created to improve signal integrity of the data
transmission across the memory bus. This termination scheme is essential to prevent data error
from signal reflections while transmitting at high frequencies encountered with DDR-SDRAM.
The DDR-SDRAM memory termination structure determines the main characteristics of the VT
rail, which is to be able to sink and source current while maintaining acceptable VTT tolerance.
Fig. 6-1 shows typical characteristics for a single memory cell.
When Q1 is on and Q2 is off:
z Current flows from VDDQ via the termination resistor to VTT
z VTT sinks current
Publication Date: Nov., 2011
-3- Revision A2
5 Page 
NCT3107S
7. ELECTRICAL CHARACTERISTIC
Absolute Maximum Ratings
PARAMETER
RATING
UNIT
Power Pins AVIN, PVIN, VDDQ
-0.3 to 6V
V
Voltage on Other Pins
-0.3 to 6V
V
Junction Temperature
Storage Temperature
Soldering Temperature
Human Body Mode
ESD Protection
Machine Mode
150
-50 to 150
Refer to IPC/JEDEC J-STD-020 Specification
2
200
°C
°C
kV
V
Latch-up
100 mA
Note1. No pin should exceed AVIN.
Note2. Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device.
These are stress ratings only and functional operation of the device at these or any other conditions beyond
those indicated under recommended operating conditions is not implied. Exposure to absolute maximum rated
conditions for extended periods may affect device reliability.
Note3. Devices are ESD sensitive. Handling precaution recommended.
Thermal Information
ITEM
RATING
UNIT
Power Dissipation, PD @ TA=25℃
1.33 W
Package Thermal Resistance, ESOP8, θJA
75 ℃/W
Note1. At elevated temperatures, devices must be de-rated based on thermal resistance. The device in the ESOP-8
package must be de-rated at θJA=75˚C/W junction to ambient with minimum PCB footprint.
Recommended Operating Conditions
PARAMETER
Operating Temperature
Junction Temperature
Supply Voltage, AVIN
Capacitance of AVIN Decoupling Capacitor
Capacitance of PVIN Decoupling Capacitor
Capacitance of VDDQ Decoupling Capacitor
Capacitance of VREF Regulation Capacitor
Capacitance of VTT Regulation Capacitor
RATING
-40 to 85
-40 to 125
2.2 to 5.5
0.1 to 4.7
10 to 270
0.1 to 270
0.01 to 0.1
10 to 470
UNIT
°C
°C
V
uF
uF
uF
uF
uF
Publication Date: Nov., 2011
-9- Revision A2
11 Page | ||
| Páginas | Total 21 Páginas | |
| PDF Descargar | [ Datasheet NCT3107S.PDF ] | |
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