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PDF NAU88C22 Data sheet ( Hoja de datos )
| Número de pieza | NAU88C22 | |
| Descripción | 24-bit Stereo Audio Codec | |
| Fabricantes | nuvoton | |
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NAU88C22
24-bit Stereo Audio Codec with Speaker Driver
Description
The NAU88C22 is a low power, high quality CODEC for portable and general purpose audio applications. In
addition to precision 24-bit stereo ADCs and DACs, this device integrates a broad range of additional functions
to simplify implementation of complete audio system solutions. The NAU88C22 includes drivers for speaker,
headphone, and differential or stereo line outputs, and integrates preamps for stereo differential microphones,
significantly reducing external component requirements. Also, a fractional PLL is available to accurately
generate any audio sample rate for the CODEC using any commonly available system clock from 8MHz through
33MHz.
Advanced on-chip digital signal processing includes a 5-band equalizer, a 3-D audio enhancer, a mixed-signal
automatic level control for the microphone or line input through the ADC, and a digital limiter/dynamic-range-
compressor (DRC) function for the playback path. Additional digital filtering options are available in the ADC
path, to simplify implementation of specific application requirements such as “wind noise reduction” and speech
band enhancement. The digital audio input/output interface can operate as either a master or a slave.
The NAU88C22 operates with analog supply voltages from 2.5V to 3.6V, while the digital core can operate at
1.7V to conserve power. The loudspeaker BTL output pair and two auxiliary line outputs can operate using a 5V
supply to increase output power capability, enabling the NAU88C22 to drive 1 Watt into an external speaker.
Internal register controls enable flexible power saving modes by powering down sub-sections of the chip under
software control.
The NAU88C22 is specified for operation from -40°C to +85°C, and is available in a space-saving 32-lead QFN
package.
Key Features
DAC: 89dB SNR and -84dB THD (“A” weighted)
ADC: 89dB SNR and -78dB THD (“A” weighted)
Integrated BTL speaker driver: 1W into 8Ω
Integrated head-phone driver: 40mW into 16Ω
Integrated programmable microphone amplifier
Integrated line input and line output
On-chip PLL
Integrated DSP with specific functions:
5-band equalizer
3-D audio enhancement
Input automatic level control (ALC/AGC)/limiter
Output dynamic-range-compressor/limiter
Notch filter and high pass filter
Standard audio interfaces: PCM and I2S
Serial control interfaces with read/write capability
Real time readback of signal level and DSP status
Supports any sample rate from 8kHz, 48kHz,
96kHz and 192kHz
Applications
Personal Media Players
Smartphones
Personal Navigation Devices
Portable Game Players
Camcorders
Digital Still Cameras
Portable TVs
Stereo Bluetooth Headsets
NAU88C22 Datasheet Rev 0.6
Page 1 of 101
June, 2016
1 page  
Electrical Characteristics
Conditions: VDDC = 1.8V, VDDA = VDDB = VDDSPK = 3.3V (VDDSPK = 1.5*VDDA when Boost), MCLK =
12.288MHz, TA = +25°C, 1kHz signal, fs = 48kHz, 24-bit audio data, 64X oversampling rate, unless otherwise stated.
Parameter
Symbol Comments/Conditions Min Typ Max
Analog to Digital Converter (ADC)
Full scale input signal 1
VINFS
PGABST = 0dB
PGAGAIN = 0dB
Signal-to-noise ratio
Total harmonic distortion 2
SNR Gain = 0dB, A-weighted
THD+N Input = -3dB FS input
Channel separation
1kHz input signal
Digital to Analog Converter (DAC) driving RHP / LHP with 10kΩ / 50pF load
Full-scale output
Gain paths all at 0dB gain
1.0
0
89
-78
106
VDDA / 3.3
Units
Vrms
dBV
dB
dB
dB
Vrms
Signal-to-noise ratio
Total harmonic distortion 2
Channel separation
SNR
THD+N
A-weighted
RL = 10kΩ; full-scale signal
1kHz input signal
Output Mixers
Maximum PGA gain into mixer
Minimum PGA gain into mixer
PGA gain step into mixer
Guaranteed monotonic
Speaker Output (RSPKOUT / LSPKOUT with 8Ω bridge-tied-load) 7
Full scale output 4
SPKBST = 1,
VDDSPK=VDDA
SPKBST = 0
Total harmonic distortion 2
THD+N
VDDSPK= 1.5 * VDDA
Po = 200mW,
VDDSPK=3.3V
Po = 320mW,
VDDSPK = 3.3V
Po = 860mW,
VDDSPK = 1.5 * VDDA
Po = 1000mW,
VDDSPK = 1.5 * VDDA
Signal-to-noise ratio
SNR VDDSPK = 3.3V
88 89
-84
100
+6
-15
3
VDDA / 3.3
(VDDA / 3.3) * 1.5
-64
-65
-59
-37
96
dB
dB
dB
dB
dB
dB
Vrms
Vrms
dB
dB
dB
dB
dB
VDDSPK=1.5 * VDDA
94 dB
Power supply rejection ratio
(50Hz - 22kHz)
PSRR
VDDSPK = 3.3V
VDDSPK = 1.5 * VDDA
Analog Outputs (RHP / LHP; RSPKOUT / LSPKOUT)
Maximum programmable gain
Minimum programmable gain
Programmable gain step size
Guaranteed monotonic
Mute attenuation
1kHz full scale signal
80 dB
76 dB
+6 dB
-57 dB
1 dB
85 dB
NAU88C22 Datasheet Rev 0.6
Page 5 of 101
June, 2016
5 Page 
11.4 Supply Currents of Specific Blocks.............................................................................................................66
12 APPENDIX A: DIGITAL FILTER CHARACTERISTICS ............................................................................67
13 APPENDIX B: COMPANDING TABLES .....................................................................................................73
13.1 µ-Law / A-Law Codes for Zero and Full Scale ............................................................................................73
13.2 µ-Law / A-Law Output Codes (Digital mW).................................................................................................73
14 APPENDIX C: DETAILS OF REGISTER OPERATION ..............................................................................74
15 APPENDIX D: REGISTER OVERVIEW.......................................................................................................94
16 PACKAGE DIMENSIONS ..............................................................................................................................96
17 ORDERING INFORMATION .........................................................................................................................99
NAU88C22 Datasheet Rev 0.6
Page 11 of 101
June, 2016
11 Page | ||
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| PDF Descargar | [ Datasheet NAU88C22.PDF ] | |
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