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PDF NAU8500 Data sheet ( Hoja de datos )

Número de pieza NAU8500
Descripción 24-bit Mono Audio ADC
Fabricantes nuvoton 
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NAU8500
1. GENERAL DESCRIPTION
24-bit Mono Audio ADC with 2-wire Interface Control
emPowerAudio
NAU8500 is a cost effective and low power wideband MONO audio ADC. This device integrates a broad range of
additional functions to simplify the implementation of complete audio systems. Functions include Automatic Level
Control (ALC) with noise gate, PGA, standard audio interface I2S, PCM with time slot assignment, and on-chip
PLL. The device provides one differential microphone input and few variable gain control stages in the audio path.
The analog inputs have PGA on the front end, allowing dynamic range optimization with a wide range of input
sources. In addition to a digital high pass filter to remove DC offset voltages, the ADC also features voice band
digital filtering. NAU8500 operates at supply voltages from 2.5V to 3.6V, although the digital core can operate at
voltage as low as 1.71V to save power. The NAU8500 is specified for operation from -40°C to +85°C, and is
available with full automotive AEC-Q100 and TS16949 qualification. It is packaged in cost effective, space-
efficient 20- lead QFN package.
2. FEATURES
24-bit signal processing linear Audio ADC
Audio ADC: 91dB SNR and -80dB THD
Support variable sample rates from 8kHz - 48kHz
Analog I/O
Integrated programmable Microphone Amplifier
Low Noise bias supplied for microphone
On-chip PLL
Interfaces
I2S digital interface PCM time slot assignment
2-Wire serial control Interface (I2C style; /Write capable)
Low Power, Low Voltage
Analog Supply: 2.5V to 3.6V
Digital Supply: 1.71V to 3.6V
Nominal Operating Voltage: 3.3V
Additional features
5-band Graphic Equalizer
Programmable ALC
ADC Notch Filter
Programmable High Pass Filter
AEC-Q100 & TS16949 qualification
Industrial temperature: range: 40C to +85C
Applications
Audio Recording devices
Security Systems
Video and Still Cameras
Enhanced Audio inputs for SOC products
Gaming Systems
emPowerAudio
Datasheet Revision 1.7
Page 1 of 88
June, 2014

1 page




NAU8500 pdf
NAU8500
6. Table of Contents
1. GENERAL DESCRIPTION ..................................................................................................................................1
2. FEATURES .........................................................................................................................................................1
3. PIN CONFIGURATION .......................................................................................................................................2
4. PIN DESCRIPTION .............................................................................................................................................3
5. BLOCK DIAGRAM...............................................................................................................................................4
6. TABLE OF CONTENTS ......................................................................................................................................5
7. LIST OF FIGURES ..............................................................................................................................................8
8. LIST OF TABLES ..............................................................................................................................................10
9. ABSOLUTE MAXIMUM RATINGS ....................................................................................................................11
10. OPERATING CONDITIONS ..............................................................................................................................11
11. ELECTRICAL CHARACTERISTICS..................................................................................................................12
12. FUNCTIONAL DESCRIPTION ..........................................................................................................................15
12.1. INPUT PATH ..............................................................................................................................................15
12.1.1. The differential microphone input (MIC- & MIC+ pins) ........................................................................16
12.1.2. PGA Boost Stage ................................................................................................................................18
12.2. MICROPHONE BIASING ...........................................................................................................................19
12.3. ADC DIGITAL FILTER BLOCK ..................................................................................................................21
12.3.1. Programmable High Pass Filter (HPF) ................................................................................................22
12.3.2. Programmable Notch Filter (NF) .........................................................................................................22
12.3.3. Digital ADC Gain Control.....................................................................................................................23
12.4. PROGRAMMABLE GAIN AMPLIFIER (PGA) ............................................................................................23
12.4.1. Automatic level control (ALC)..............................................................................................................23
12.4.2. Peak Limiter Mode ..............................................................................................................................27
12.4.3. Attack Time .........................................................................................................................................28
12.4.4. Decay Times .......................................................................................................................................28
12.4.5. Noise gate (normal mode only) ...........................................................................................................28
12.4.6. Zero Crossing......................................................................................................................................29
12.4.7. 5-Band Equalizer.................................................................................................................................30
12.4.8. Slow Timer Clock ................................................................................................................................31
12.5. CLOCK GENERATION BLOCK .................................................................................................................32
12.6. CONTROL INTERFACE ............................................................................................................................36
12.6.1. 2-WIRE Serial Control Mode (I2C Style Interface) ...............................................................................36
12.7. DIGITAL AUDIO INTERFACES .................................................................................................................39
12.7.1. Right Justified audio data ....................................................................................................................40
12.7.2. Left Justified audio data ......................................................................................................................41
12.7.3. I2S audio data......................................................................................................................................42
12.7.4. PCM audio data ..................................................................................................................................43
12.7.5. PCM Time Slot audio data ..................................................................................................................44
12.7.6. Companding........................................................................................................................................45
12.8. POWER SUPPLY.......................................................................................................................................46
12.8.1. Power-On Reset..................................................................................................................................46
12.8.2. Power Related Software Considerations.............................................................................................46
12.8.3. Software Reset....................................................................................................................................47
12.8.4. Power Up/Down Sequencing ..............................................................................................................47
12.8.5. Reference Impedance (REFIMP) and Analog Bias .............................................................................48
emPowerAudio
Datasheet Revision 1.7
Page 5 of 88
June, 2014

5 Page





NAU8500 arduino
NAU8500
9. ABSOLUTE MAXIMUM RATINGS
CONDITION
VDDD, VDDA supply voltages
Core Digital Input Voltage range
Analog Input Voltage range
Industrial operating temperature
Storage temperature range
MIN
-0.3
VSSD 0.3
VSSA 0.3
-40
-65
MAX
+3.63
VDDD + 0.30
VDDA + 0.30
+85
+150
Units
V
V
V
0C
0C
CAUTION: Do not operate at or near the maximum ratings listed for extended period of time. Exposure to such
conditions may adversely influence product reliability and result in failures not covered by warranty. These
devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
10. OPERATING CONDITIONS
Condition
Analog supplies range
Digital supply range (Core)
Ground
1. VDDA must be ≥ VDDD.
Symbol
VDDA
VDDD
VSSD, VSSA
Min Value
2.501
1.71
Typical
Value
0
Max Value Units
3.60 V
3.60 V
V
emPowerAudio
Datasheet Revision 1.7
Page 11 of 88
June, 2014

11 Page







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