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PDF NAU8224 Data sheet ( Hoja de datos )
| Número de pieza | NAU8224 | |
| Descripción | 3.1W Stereo Filter-Free Class-D Audio Amplifier | |
| Fabricantes | nuvoton | |
| Logotipo |  |
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NAU8224
3.1W Stereo Filter-Free Class-D Audio Amplifier
with 2 wire interface gain control
1 Description
The NAU8224 is a stereo high efficiency filter-free Class-D audio amplifier, which is capable of driving a 4Ω load with
up to 3.1W output power. This device provides chip enable pin with extremely low standby current and fast start-up time
of 3.4ms. The NAU8224 features a highly flexible 2 wire interface with many useful gain settings. The gain can be
selected from 24dB to -62dB (plus mute) by using 2 wire interface and GS pin.
The NAU8224 is ideal for the portable applications of battery drive, as it has advanced features like 87dB PSRR, 91%
efficiency, ultra low quiescent current (i.e. 2.1mA at 3.7V for 2 channels) and superior EMI performance. It has the
ability to configure the inputs in either single-ended or differential mode. NAU8224 is available in Miniature QFN-20
package.
Key Features
Low Quiescent Current:
• 2.1mA at 3.7V for 2 channels
• 3.2mA at 5V for 2 channels
Gain Setting with 2 wire interface and GS pin
• 24dB to -62dB (plus mute)
Powerful Stereo Class-D Amplifier:
• 2ch x 3.1W (4Ω @ 5V, 10% THD+N)
• 2ch x 1.26W (4Ω @ 3.7V, 1% THD+N)
• 2ch x 1.76W (8Ω @ 5V, 10% THD+N)
• 2ch x 0.76W (8Ω @ 3.7V, 1% THD+N)
Low Output Noise: 20 µVRMS @0dB gain
87dB PSRR @217Hz
Low Current Shutdown Mode
Click-and Pop Suppression
Applications
Notebooks / Tablet PCs
Personal Media Players / Portable TVs
MP3 Players
Portable Game Players
Digital Camcorders
NAU8224 Datasheet Rev 1.0
Figure 1: NAU8224Block Diagram
Page 1 of 27
Aug, 2012
1 page  
Electrical Characteristics (continued)
Conditions: EN = VDD = 5V, VSS = 0V, Av = 12dB, ZL = ∞, Bandwidth = 20Hz to 22kHz, TA = 25 °C
Parameter
Symbol Comments/Conditions Min Typ Max
Normal Operation
Quiescent Current Consumption
Shut Down Current
Oscillator Frequency
Efficiency
Start Up Time
Output Offset Voltage
Common Mode Rejection Ratio
Click-and-Pop Suppression
Power Supply Rejection Ratio
IQUI
IOFF
fOSC
η
Tstart
VOS
CMRR
DC
PSRR
AC
PSRR*
VDD = 3.7V
VDD = 5V
EN = 0
fIN = 1kHz
Into Shutdown (ZL=8Ω)
A Weighted
VDD = 2.5V to 5.5V
VRIPPLE =
0.2Vpp@217Hz**
VRIPPLE = 0.2Vpp@1KHz
VRIPPLE =
0.2Vpp@10KHz
2.1
3.17
0.1
300
91
3.4
±1 ±4
80
-72
98
87
74
54
Units
mA
mA
µA
kHz
%
msec
mV
dB
dBV
dB
dB
Channel Crosstalk
fIN = 1kHz,
ZL = 8Ω + 68µH
*Measured with 0.1uF capacitor on VDD and Battery supply
-101 dB
** Measured with 2.2uF input capacitor.
Parameter
Noise Performance
Symbol Comments/Conditions Min
Av = 0dB (A-weighted)
Av = 6dB (A-weighted)
Av = 12dB (A-weighted)
Av = 18dB (A-weighted)
Av = 24dB (A-weighted)
Typ Max
20
21
27
36
52
Units
µ VRMS
The following setup is used to measure the above parameters
NAU8224Datasheet Rev 1.0
Page 5 of 27
Aug, 2012
5 Page 
0
1
0
1
0
1
0
R/W
Device
Address Byte
A7
A6
A5
A4
A3
A2
A1
A0
Control
Address Byte
D7 D6 D5 D4 D3 D2 D1 D0 Data Byte
Slave Address Byte, Control Address Byte, and Data Byte
6.1.3 2-Wire Write Operation
A Write operation consists of a two-byte instruction followed by a Data Byte. A Write operation requires a START
condition, followed by a valid device address byte with R/W= 0, a valid control address byte, data byte, and a STOP
condition.
The NAU8224 is permanently programmed with “010 1010” (0x2A) as the Device Address. If the Device Address
matches this value, the NAU8224 will respond with the expected ACK signaling as it accepts the data being transmitted
into it.
Write Sequence
6.1.4 2-Wire Single Read Operation
A Read operation consists of a three-byte Write instruction followed by a Read instruction of data byte. The bus master
initiates the operation issuing the following sequence: a START condition, device address byte with the R/W bit set to
“0”, and a Control Register Address byte. This indicates to the slave device which of its control registers is to be
accessed.
The NAU8224 is permanently programmed with “010 1010” (0x2A) as its device address. If the device address matches
this value, the NAU8224 will respond with the expected ACK signaling as it accepts the Control Register Address being
transmitted into it. After this, the master transmits a second START condition, and a second instantiation of the same
device address, but now with R/W=1.
After again recognizing its device address, the NAU8224 transmits an ACK, followed by a one byte value containing the
data from the selected control register inside the NAU8224. During this phase, the master generates the ACK signaling
with byte transferred from the NAU8224.
NAU8224Datasheet Rev 1.0
Page 11 of 27
Aug, 2012
11 Page | ||
| Páginas | Total 27 Páginas | |
| PDF Descargar | [ Datasheet NAU8224.PDF ] | |
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