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PDF N78E366A Data sheet ( Hoja de datos )
| Número de pieza | N78E366A | |
| Descripción | 8-bit 8051-based Microcontroller | |
| Fabricantes | nuvoton | |
| Logotipo |  |
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Nuvoton 8-bit 8051-based Microcontroller
N78E366A
Data Sheet
1 page  
2. FEATURES
Fully static design 8-bit CMOS microcontroller.
Wide supply voltage of 2.4V to 5.5V and wide frequency from 4MHz to 40MHz.
12T mode compatible with the tradition 8051 timing.
6T mode supported for double performance.
On-chip RC oscillator of 22.1184MHz/11.0592MHz, trimmed to ±1% at room temperature for the precise
system clock.
64k bytes Flash APROM for the application program.
2.5k bytes Flash LDROM for ISP code.
In-System-Programmable (ISP) built in. ISP Erasing or programming supports wide operating voltage
3.0V~5.5V.
Flash 10,000 writing cycle endurance. Greater than 10 years data retention under 85℃.
256 bytes of on-chip RAM.
1k bytes of on-chip auxiliary RAM (XRAM).
64k bytes Program Memory address space and 64k bytes Data Memory address space.
Maximum five 8-bit general purpose I/O ports pin-to-pin compatible with standard 8051, additional INT2
and INT3 on packages except DIP-40.
Three 16-bit Timers/Counters.
One dedicate timer for Power Down mode waking-up.
One full-duplex UART port.
Five pulse width modulated (PWM) output channels.
One SPI communication port.
11-source, 4-priority-level interrupts capability.
Programmable Watchdog Timer.
Power-on reset.
Brown-out detection interrupt and reset, 4-level selected.
Supports software reset function.
Built-in power management with Idle mode and Power Down mode.
Code lock for data security.
Publication Release Date: March 11, 2011
- 5 - Revision: V2.0
5 Page 
Table 4–1. Pin Description
Pin number
Alternate Function
Symbol
Type[1]
DIP PLCC PQFP LQFP
12
Description
connecting an external capacitor to VDD.
39 43 37 40 P0.0
38 42 36 39 P0.1
37 41 35 38 P0.2
36 40 34 37 P0.3
35 39 33 35 P0.4
AD0 D, I/O PORT0: Port 0 is an 8-bit open-drain port by default.
Via setting P0UP (P0OR.0), P0 will switch as weakly
AD1 D, I/O pulled up internally.
AD2
D, I/O
P0 has an alternative function as AD[7:0] while ex-
ternal memory accessing. During the external
AD3 D, I/O memory access, P0 will output high will be internal
strong pulled-up rather than weak pull-up in order to
AD4 D, I/O drive out high byte address for external devices.
34 38 32 34 P0.5
AD5 D, I/O
33 37 31 33 P0.6
AD6 D, I/O
32 36 30 32 P0.7
1 2 40 43 P1.0 T2
2 3 41 44 P1.1 T2EX
AD7
D, I/O
I/O PORT1: Port 1 is an 8-bit quasi bi-directional I/O
port. Its multifunction pins are for T2, T2EX,
I/O PWM0~PWM4, SS , MOSI, MISO, and SPCLK.
3 4 42 45 P1.2
I/O
4 5 43 46 P1.3 PWM0
I/O
5 6 44 47 P1.4 PWM1 SS I/O
6 7 1 1 P1.5 PWM2 MOSI I/O
7 8 2 2 P1.6 PWM3 MISO I/O
8 9 3 3 P1.7 PWM4 SPCLK I/O
21 24 18 19 P2.0
22 25 19 20 P2.1
23 26 20 21 P2.2
24 27 21 22 P2.3
A8 I/O PORT2: Port 2 is an 8-bit quasi bi-directional I/O
port. It has an alternative function as A[15:8] while
A9 I/O external memory accessing. During the external
memory access, P2 will output high will be internal
A10 I/O strong pulled-up rather than weak pull-up in order to
drive out high byte address for external devices.
A11 I/O
25 28 22 23 P2.4
A12 I/O
26 29 23 25 P2.5
A13 I/O
27 30 24 26 P2.6
A14 I/O
28 31 25 27 P2.7
A15 I/O
- 11 -
Publication Release Date: March 11, 2011
Revision: V2.0
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet N78E366A.PDF ] | |
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