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PDF ADAQ7988 Data sheet ( Hoja de datos )
| Número de pieza | ADAQ7988 | |
| Descripción | Integrated Data Acquisition Subsystem | |
| Fabricantes | Analog Devices | |
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Data Sheet
FEATURES
Easy to use
Integrated data acquisition subsystem
All active components designed by Analog Devices, Inc.
On-board ADC driver and reference buffer
50% PCB area savings
Includes critical passive components
SPI-/QSPI-/MICROWIRE™-/DSP-compatible serial interface
Daisy-chain multiple ADAQ7980/ADAQ7988 devices
Versatile supply configuration with 1.8 V/2.5 V/3 V/5 V
logic interface
Pseudo differential ADC input structure
High performance
16-bit resolution with no missing codes
Throughput: 1 MSPS (ADAQ7980) and 500 kSPS (ADAQ7988)
INL: ±8 ppm typical and 20 ppm maximum
SNR: 91.5 dB typical at 10 kHz (unity gain)
THD: −105 dB at 10 kHz
Low input bias current: 470 nA typical
Low power dissipation
21 mW typical at 1 MSPS (ADAQ7980)
16.5 mW typical at 500 kSPS (ADAQ7988)
Flexible power-down modes
Dynamic power scaling
Small, 24-lead, 5 mm × 4 mm LGA package
Wide operating temperature range: −55°C to +125°C
APPLICATIONS
Automated test equipment (ATE)
Battery powered instrumentation
Communications
Data acquisition
Process control
Medical instruments
GENERAL DESCRIPTION
The ADAQ7980/ADAQ7988 are 16-bit analog-to-digital converter
(ADC) subsystems that integrate four common signal processing
and conditioning blocks into a system in package (SiP) design
that supports a variety of applications. These devices contain
the most critical passive components, eliminating many of the
design challenges associated with traditional signal chains that
use successive approximation register (SAR) ADCs. These passive
components are crucial to achieving the specified device
performance.
16-Bit, 1 MSPS, Integrated Data
Acquisition Subsystem
ADAQ7980/ADAQ7988
FUNCTIONAL BLOCK DIAGRAM
V+ REF REF_OUT LDO_OUT VDD
PD_REF
10µF
LDO
2.2µF
PD_LDO
IN+
IN–
AMP_OUT
20Ω
1.8nF
ADC
ADAQ7980/
ADAQ7988
VIO
SDI
SCK
SDO
CNV
V– PD_AMP ADCN GND
Figure 1.
The ADAQ7980/ADAQ7988 contain a high accuracy, low power,
16-bit SAR ADC, a low power, high bandwidth, high input
impedance ADC driver, a low power, stable reference buffer,
and an efficient power management block. Housed within a tiny,
5 mm × 4 mm LGA package, these systems simplify the design
process for data acquisition systems. The level of system integration
of the ADAQ7980/ADAQ7988 solves many design challenges,
while the devices still provide the flexibility of a configurable
ADC driver feedback loop to allow gain and/or common-mode
adjustments. A set of four device supplies provides optimal system
performance; however, single-supply operation is possible with
minimal impact on device operating specifications.
Using the SDI input, the serial peripheral interface (SPI)-
compatible serial interface features the ability to daisy-chain
multiple devices on a single, 3-wire bus and provides an optional
busy indicator. The user interface is compatible with 1.8 V, 2.5 V,
3 V, or 5 V logic.
Specified operation of these devices is from −55°C to +125°C.
Table 1. Integrated SAR ADC Subsystems
Type
500 kSPS
1000 kSPS
16-Bit
ADAQ7988
ADAQ7980
Rev. 0
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
©2017 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
1 page  
Data Sheet
Parameter
Input Current
Low (IIL)
High (IIH)
DIGITAL OUTPUTS
Data Format
Pipeline Delay
VOL
VOH
POWER-DOWN SIGNALING
ADC Driver/REF Buffer
PD_AMP, PD_REF Voltage
Low
High
Turn-Off Time
Turn-On Time
Dynamic Power Scaling Period
Low Dropout (LDO) Regulator
PD_LDO Voltage
Low
High
PD_LDO Logic Hysteresis
Turn-Off Time
Turn-On Time
POWER REQUIREMENTS
VDD
LDO Voltage Accuracy
LDO Line Regulation
LDO Load Regulation
LDO Start-Up Time
LDO Current-Limit Threshold
LDO Thermal Shutdown
Threshold
Hysteresis
LDO Dropout Voltage
V+
V−
VIO
Total Standby Current1, 2
ADAQ7980 Current Draw
VIO
V+/V−
VDD
Test Conditions/Comments
ISINK = 500 µA
ISOURCE = −500 µA
Powered down
Enabled
50% of PD_AMP, PD_REF to <10% of
enabled quiescent current
Specified performance
Specified performance
Powered down
Enabled
2.2 µF capacitive load
ILDO_OUT = 10 mA, TA = 25°C
100 µA < ILDO_OUT < 100 mA,
VDD = 3.5 V to 10 V
VDD = 3.5 V to 10 V
ILDO_OUT = 100 µA to 100 mA
VLDO_OUT = 2.5 V
TJ rising
ILDO_OUT = 10 mA
ILDO_OUT = 100 mA
Static, all devices enabled
ADC driver, REF buffer disable
ADC driver, REF buffer, LDO disable
1 MSPS
ADAQ7980/ADAQ7988
Min Typ Max
−1 +1
−1 +1
Serial 16 bits, straight binary
Conversion results available
immediately after completed
conversion
0.4
VIO − 0.3
Unit
µA
µA
V
V
<2.2
>2.6
1.25 2.75
V
V
µs
2
10
7.25 µs
µs
1.06
1.15
3.5
−0.8
−1.8
−0.015
250
3.7
V+ − 10
1.7
1.12
1.22
100
460
370
5
0.002
380
360
150
15
30
200
7
−2
1.2
56
14
0.3
1.5
1.45
1.18
1.30
650
425
10
+0.8
+1.8
+0.015
0.004
460
60
420
V− + 10
+0.1
5.5
1.7
103
23
0.34
2.0
1.6
V
V
mV
µs
µs
V
%
%
%/V
%/mA
µs
mA
°C
°C
mV
mV
V
V
V
mA
µA
µA
mA
mA
mA
Rev. 0 | Page 5 of 49
5 Page 
Data Sheet
ADAQ7980/ADAQ7988
TIMING SPECIFICATIONS
VDD = 3.5 V to 10 V, VIO = 1.7 V to 5.5 V, and TA = −55°C to +125°C, unless otherwise noted In addition to Figure 2 and Figure 3, see
Figure 72, Figure 74, Figure 76, Figure 78, Figure 80, and Figure 82 for the additional timing diagrams detailed in Table 6.
Table 6.
Parameter
CONVERSION TIME: CNV RISING EDGE TO DATA AVAILABLE
VIO Above 3.0 V (ADAQ7980)
VIO Above 1.7 V (ADAQ7980)
ADAQ7988
ACQUISITION PHASE1
ADAQ7980
ADAQ7988
TIME BETWEEN CONVERSIONS
VIO Above 3.0 V (ADAQ7980)
VIO Above 1.7 V (ADAQ7980)
VIO Above 1.7 V (ADAQ7988)
CS MODE
CNV Pulse Width
SCK Period
VIO Above 4.5 V
VIO Above 3.0 V
VIO Above 1.7 V
CNV or SDI Low to SDO D15 MSB Valid
VIO Above 3.0 V
VIO Above 1.7 V
CNV or SDI High or Last SCK Falling Edge to SDO High Impedance
SDI Valid Hold Time from CNV Rising Edge
VIO Above 3.0 V
VIO Above 1.7 V
CHAIN MODE
SCK Period
VIO Above 4.5 V
VIO Above 3.0 V
VIO Above 1.7 V
SDI Valid Hold Time from CNV Rising Edge
SCK Valid Setup Time from CNV Rising Edge
SCK Valid Hold Time from CNV Rising Edge
SDI Valid Setup Time from SCK Falling Edge
SDI Valid Hold Time from SCK Falling Edge
SDI High to SDO High (with Busy Indicator)
VIO Above 3.0 V
VIO Above 1.7 V
SCK
Low Time
VIO Above 3.0 V
VIO Above 1.7 V
High Time
VIO Above 3.0 V
VIO Above 1.7 V
Symbol
tCONV
tACQ
tCYC
tCNVH
tSCK
tEN
tDIS
tHSDICNV
tSCK
tHSDICNV
tSSCKCNV
tHSCKCNV
tSSDISCK
tHSDISCK
tDSDOSDI
tSCKL
tSCKH
Min
500
500
500
290
800
1000
1200
2000
10
10.5
12
22
2
10
Typ Max
710
800
1200
10
40
20
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
11.5 ns
13 ns
23 ns
0 ns
5 ns
5 ns
2 ns
3 ns
15 ns
22 ns
4.5 ns
6 ns
4.5 ns
6 ns
Rev. 0 | Page 11 of 49
11 Page | ||
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