PDF KAE-02152 Data sheet ( Hoja de datos )

Número de pieza	KAE-02152
Descripción	Interline CCD Image Sensor
Fabricantes	ON Semiconductor
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No Preview Available ! KAE-02152 Advance Information 1920 (H) x 1080 (V) Interline CCD Image Sensor The KAE−02152 image sensor is a 1080p, 2/3” format Interline Transfer EMCCD that provides increased Quantum Efficiency (particularly for NIR wavelengths) without a decrease in Modulation Transfer Function (MTF) when compared to the KAE−02150. Each of the sensor’s four outputs includes both a conventional horizontal CCD register and a high gain EMCCD register. An intra−scene switchable gain feature samples each charge packet on a pixel−by−pixel basis, enabling the camera system to determine whether the charge will be routed through the normal gain output or the EMCCD output based on a user selectable threshold. This feature enables imaging in extreme low light even when bright objects are within a dark scene, allowing a single camera to capture quality images from sunlight to starlight. The device is available in two package configurations: PGA, and PGA with integrated thermoelectric cooler (TEC). Table 1. GENERAL SPECIFICATIONS Parameter Architecture Total Number of Pixels Number of Effective Pixels Number of Active Pixels Pixel Size Active Image Size Aspect Ratio Number of Outputs Charge Capacity Output Sensitivity Quantum Efficiency Peak Mono/Color (RGB) 850 nm 920 nm Read Noise (20 MHz) Normal Mode (1× Gain) Intra-Scene Mode (20× Gain) Dark Current (0°C) Photodiode, VCCD Typical Value Interline CCD; with EMCCD 2004 (H) × 1144 (V) 1960 (H) × 1120 (V) 1920 (H) × 1080 (V) 5.5 mm (H) × 5.5 mm (V) 10.56 mm (H) × 5.94 mm (V) 12.1 mm (Diag.), 2/3″ Optical Format 16:9 1, 2, or 4 20,000 e− 44 mV/e− 52% / 45% / 43% / 41% 16% 8% 9 e− rms < 1 e− rms < 0.1 e−/s, 6 e−/s Dynamic Range Normal Mode (1× Gain) Intra-Scene Mode (20× Gain) Charge Transfer Efficiency Blooming Suppression Smear Image Lag Maximum Pixel Clock Speed Maximum Frame Rate Normal Mode, Intra-Scene Mode 68 dB 86 dB 0.999999 > 1000 X −100 dB < 1 e− 40 MHz 60 fps (40 MHz), 30 fps (20 MHz) Package 135 pin PGA 143 pin PGA with TEC Cover Glass Clear Glass, Taped MAR Glass, Sealed (with TEC only) NOTE: All Parameters are specified at T = 0°C unless otherwise noted. © Semiconductor Components Industries, LLC, 2017 April, 2017 − Rev. P1 1 www.onsemi.com Figure 1. KAE−02152 Interline CCD Image Sensor ORDERING INFORMATION See detailed ordering and shipping information on page 2 of this data sheet. Features • Increased QE, with 2x Improvement at 820 nm • Intra-Scene Switchable Gain • Wide Dynamic Range • Low Noise Architecture • Exceptional Low Light Imaging • Global Shutter • Excellent Image Uniformity and MTF • Bayer Color Pattern and Monochrome • PGA, or PGA with integrated TEC Applications • Surveillance • Scientific Imaging • Medical Imaging • Intelligent Transportation This document contains information on a new product. Specifications and information herein are subject to change without notice. Publication Order Number: KAE−02152/D 1 page Physical Description Pin Grid Array and Pin Description H G F E KAE−02152 D C B A 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Figure 4. PGA Package Designations (Bottom View) Table 4. PIN DESCRIPTION Pin Label A02 V3B VCCD Bottom Phase 3 A03 N/C No Connection A04 RG2a Amplifier 2 Reset, Quadrant A A05 N/C No Connection A06 VDD23ab Amplifier 2 and 3 Supply, Quadrants A, B A07 H1BEMa EMCCD Barrier Phase 1, Quadrant A A08 H2Ba HCCD Barrier Phase 2, Quadrant A A09 GND Ground A10 H2Bb HCCD Barrier Phase 2, Quadrant B A11 H1BEMb EMCCD barrier phase 1, Quadrant B A12 VDD23ab Amplifier 2 and 3 Supply, Quadrants A, B A13 N/C No Connection A14 RG2a Amplifier 2 Reset, Quadrant B A15 N/C No Connection A16 V3B VCCD Bottom Phase 3 A17 ESD ESD Protection Disable B01 DEVID Device ID Resistor B02 V4B VCCD Bottom Phase 4 B03 VOUT1a Amplifier 1 Output, Quadrant A Description www.onsemi.com 5 5 Page KAE−02152 Table 5. PGA WITH INTEGRATED TEC PIN DESCRIPTION (continued) Pin Label Description D09 GND Ground D10 H1Sb HCCD Storage Phase 1, Quadrant B D11 H2SEMb EMCCD Storage Multiplier Phase 2, Quadrant B D12 RG3b Amplifier 3 Reset, Quadrant B D13 H2Lb HCCD Last Gate, Outputs 1,2 And 3, Quadrant B D14 H2Xb Floating Gate Exit HCCD Gate, Quadrant B D15 RG1b Amplifier 1 Reset, Quadrant B D16 VDD1b Amplifier 1 Supply, Quadrant B D17 V2B VCCD Bottom Phase 2 D18 TEC− Thermal Electric Cooler Negative Terminal E01 V2T VCCD Top Phase 2 E02 VDD1c Amplifier 1 Supply, Quadrant C E03 RG1c Amplifier 1 Reset, Quadrant C E04 H2Xc Floating Gate Exit HCCD Gate, Quadrant C E05 H2Lc HCCD Last Gate, Outputs 1,2 And 3, Quadrant C E06 RG3c Amplifier 3 Reset, Quadrant C E07 H2SEMc EMCCD Storage Multiplier Phase 2, Quadrant C E08 H1Sc HCCD Storage Phase 1, Quadrant C E09 GND Ground E10 H1Sd HCCD Storage Phase 1, Quadrant D E11 H2SEMd EMCCD Storage Multiplier Phase 2, Quadrant D E12 RG3d Amplifier 3 Reset, Quadrant B E13 H2Ld HCCD Last Gate, Outputs 1,2 And 3, Quadrant D E14 H2Xd Floating Gate Exit HCCD Gate, Quadrant D E15 RG1d Amplifier 1 Reset, Quadrant D E16 VDD1d Amplifier 1 Supply, Quadrant D E17 V2T VCCD Top Phase 2 E18 TEC+ Thermal Electric Cooler Positive Terminal F01 V1T VCCD Top Phase 1 F02 N/C No Connection F03 VSS1c Amplifier 1 Return, Quadrant C F04 VDD23cd Amplifier 2 And 3 Supply, Quadrants C, D F05 H2SW2c HCCD Output 2 Selector, Quadrant C F06 N/C No Connection F07 H1SEMc EMCCD Storage Multiplier Phase 1, Quadrant C F08 H2Sc HCCD Storage Phase 2, Quadrant C F09 GND Ground F10 H2Sd HCCD Storage Phase 2, Quadrant D F11 H1SEMd EMCCD Storage Multiplier Phase 1, Quadrant D F12 N/C No Connection F13 H2SW2d HCCD Output 2 Selector, Quadrant D F14 VDD23cd Amplifier 2 And 3 Supply, Quadrants C, D www.onsemi.com 11 11 Page

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