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PDF ADM1272 Data sheet ( Hoja de datos )
| Número de pieza | ADM1272 | |
| Descripción | High Voltage Positive Hot Swap Controller and Digital Power Monitor | |
| Fabricantes | Analog Devices | |
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Data Sheet
High Voltage Positive Hot Swap Controller
and Digital Power Monitor with PMBus
ADM1272
FEATURES
Controls supply voltages from 16 V to 80 V (absolute
maximum 120 V)
High voltage (80 V) IPC-9592 compliant packaging
<500 ns response time to short circuit
FET energy monitoring for adaptable FET SOA protection
Gate boost mode for fast recovery from OC transients
Programmable random start mode to stagger power-on
FET fault detection
Remote temperature sensing with programmable warning
and shutdown thresholds
Programmable 2.5 mV to 30 mV system current-limit setting
range
±0.85% accurate current measurement with 12-bit ADC
ILOAD, VIN, VOUT, temperature, power, and energy telemetry
Programmable start-up current limit
Programmable linear output voltage soft start
1% accurate UV and OV thresholds
Programmable hot swap restart function
2 programmable GPIO pins
Reports power and energy consumption
Peak detect registers for current, voltage, and power
PMBus fast mode compliant interface
48-lead 7 mm × 8 mm LFCSP
APPLICATIONS
48 V/54 V systems
Servers
Power monitoring and control/power budgeting
Central office equipment
Telecommunication and data communication equipment
Industrial applications
GENERAL DESCRIPTION
The ADM1272 is a hot swap controller that allows a circuit board
to be removed from or inserted into a live backplane. It also features
current, voltage, and power readback via an integrated 12-bit
analog-to-digital converter (ADC), accessed using a PMBus™
interface. This device is able to withstand up to 120 V, which
makes it very robust in surviving surges and transients commonly
associated with high voltage systems, usually clamped using
protection devices such as transient voltage suppressors (TVSs)
that can often exceed 100 V.
The load current, ILOAD, is measured using an internal current
sense amplifier that measures the voltage across a sense resistor
in the power path via the SENSE+ and SENSE− pins. A default
current limit sense voltage of 30 mV is set, but this limit can be
Rev. 0
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adjusted down, if required, using a resistor divider network
from the VCAP regulator output voltage to the ISET pin. An
additional resistor can also be placed from ISET to VIN (or VOUT) to
allow the current limit to track inversely with the rail voltage.
This resistor allows an approximate system power limit to be used.
The ADM1272 limits the current through the sense resistor by
controlling the gate voltage of an external N channel field effect
transistor (FET) in the power path. The sense voltage, and there-
fore the load current, is maintained below the preset maximum.
The ADM1272 protects the external FET by monitoring and
limiting the energy transfer through the FET while the current is
being controlled. This energy limit is set by the choice of compo-
nents connected to the EFAULT pin (for fault protection mode)
and the ESTART pin during startup. Therefore, different energy
limits can be set for start-up and normal fault conditions.
During startup, inrush currents are maintained very low and
different areas of the safe operating area (SOA) curve are of
interest, whereas during fault conditions, the currents can be
much higher.
The controller uses the drain to source voltage (VDS) across the
FET to set the current profile of the EFAULT and ESTART pins
and, therefore, the amount of much energy allowed to be
transferred in the FET. This energy limit ensures the MOSFET
remains within the SOA limits. Optionally, use a capacitor on
the DVDT pin to set the output voltage ramp rate, if required.
In case of a short-circuit event, a fast internal overcurrent
detector responds in hundreds of ns and signals the gate to shut
down. A 1.5 A pull-down device ensures a fast FET response. The
gate then recovers control within 50 µs to ensure minimal
disruption during conditions, such as line steps and surges. The
ADM1272 features overvoltage (OV) and undervoltage (UV)
protection, programmed using external resistor dividers on the
UVH, UVL, and OV pins. The use of two pins for undervoltage
allows independent accurate rising and falling thresholds. The
PWRGD output pin signals when the output voltage is valid and
the gate is sufficiently enhanced. The validity of VOUT is
determined using the PWGIN pin.
The 12-bit ADC measures the voltage across the sense resistor,
the supply voltage on the SENSE+ pin, the output voltage, and
the temperature using an external NPN/PNP device. A PMBus
interface allows a controller to read data from the ADC. As
many as 16 unique I2C addresses can be selected, depending on
how the two ADRx pins are connected. The ADM1272 is available
in a custom 48-lead LFCSP (7 mm × 8 mm) with a pinstrap mode
that allows the device to be configured for automatic retry or
latchoff when an overcurrent (OC) fault occurs.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
©2017 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
1 page  
Data Sheet
ADM1272
SPECIFICATIONS
VCC = 16 V to 80 V, VCC ≥ VSENSE+, VSENSE+ = 16 V to 80 V, VΔSENSE = (VSENSE+ − VSENSE−) = 0 V, TJ= −40°C to +125°C, unless otherwise noted.
Table 1.
Parameter
POWER SUPPLY
Operating Voltage Range1
Undervoltage Lockout
Undervoltage Hysteresis
Quiescent Current
Power-On Reset (POR)
UVL AND UVH PINS
Input Current
UVH Threshold
UVL Threshold
UVx Threshold Hysteresis
UVx Glitch Filter
UVx Propagation Delay
OV PIN
Input Current
OV Threshold
OV Hysteresis Current
OV Glitch Filter
OV Propagation Delay
SENSE+ AND SENSE− PINS
Current-Limit Setting Range
Input Current
Input Imbalance
VREG PIN
Internally Regulated Voltage
VCAP PIN
Internally Regulated Voltage
ISET PIN
Reference High Limit1
Symbol
VCC
VCCUV
VCCUVHYS
ICC
tPOR
IUV
UVHTH
UVLTH
UVHYST
UVGF
UVPD
IOV
OVTH
IOVHYST
OVGF
OVPD
VSENSECL
ISENSEx
IΔSENSE
VVREG
VVCAP
VCLREF_HI
Reference Low Limit1
VCLREF_LO
Gain of Current Sense
Amplifier1
Input Current
ISTART PIN
Reference Select Threshold
Internal Reference1
Input Current
GATE PIN3
Gate Drive Voltage
AVCSAMP
IISET
VISTARTRSTH
VCLREF1V
IISTART
ΔVGATE
Min Typ
16
13
70
27
0.99
0.887
3.5
1
1.0
0.9
100
5
0.99 1.0
4.5 5.25
1.75
3
2.5
130
4.5 5
2.68 2.7
1.2
100
40
1.35 1.5
1
10 12
4.5
Max
80
16
115
6
50
1.01
0.913
7.5
8
50
1.01
6
3.75
4.5
30
170
5
5.5
2.72
100
1.65
100
14
Unit Test Conditions/Comments
V
V VCC rising
mV
mA GATE on and power monitor running
ms
nA UVL ≤ 3.6 V, when UVL and UVH are tied together
V UV rising
V UV falling
mV When UVL and UVH are tied together
μs 50 mV overdrive
μs UVx low to GATE pull-down active
nA OV ≤ 3.6 V
V OV rising
μA
μs 50 mV overdrive
μs OV high to GATE pull-down active
mV Adjustable using ISET and ISTART pins
μA Per individual pin
μA IΔSENSE = (ISENSE+) − (ISENSE−)
V 0 µA ≤ IVREG ≤ 100 µA; CVREG = 1 μF
V 0 µA ≤ IVCAP ≤ 100 µA; CVCAP = 1 μF
V VCLREF2 = VVCAP − VISET; VSENSECL = 30 mV; internally clamped
with falling VISET
mV Internally clamped with rising VISET or VISTART < 100 mV,
VCLREF = VVCAP – VISET; VSENSECL = 2.5 mV
V/V
nA VISET ≤ VVCAP
V If VISTART > VISTARTRSTH, internal 1 V reference (VCLREF1V) is used
V
nA VISTART ≤ VVCAP
ΔVGATE = VGATE − VOUT
V 80 V ≥ VCC ≥ 20 V; IGATE ≤ 5 μA
V 20 V ≥ VCC ≥ 16 V; IGATE ≤ 5 μA
Rev. 0 | Page 5 of 57
5 Page 
Data Sheet
ABSOLUTE MAXIMUM RATINGS
Table 4.
Parameter
Rating
VCC, SENSE± to GND
VΔSENSE (SENSE+ − SENSE−)
VOUT to GND
VCP to GND
GATE (Internal Supply Only)1 to
GND
DVDT to GND
UVH, UVL, OV, MCB to GND
ISTART, ISET, VCAP to GND
ESTART, EFAULT, TEMP+ to GND
VREG (Internal Supply Only) to
GND
FAULT, RESTART to GND
−0.3 V to +120 V
−1 V to +1 V
−5 V to +120 V
−0.3 V to (VOUT + 12 V) or
(VCC + 15 V), whichever is lower
(VOUT − 0.3 V) to (VCP + 0.3 V)
(VOUT − 0.3 V) to (GATE + 0.3 V)
−0.3 V to +6.5 V
−0.3 V to +4 V
−0.3 V to VCAP + 0.3 V
−0.3 V to +5.5 V
−0.3 V to +20 V
PWGIN, SCL, SDAO, SDAI, ADR0,
ADR1 to GND
RND to GND
ENABLE, GPIO1/ALERT1/CONV,
GPIO2/ALERT2, PWRGD to GND
−0.3 V to +6.5 V
−0.3 V to VCAP + 0.3 V
−0.3 V to +20 V
TEMP− Pin to GND (Internally
Connected to GND)
Continuous Current into Any Pin
Storage Temperature Range
Operating Temperature Range (TJ)
Lead Temperature, Soldering
(10 sec)
Junction Temperature
0V
±10 mA
−65°C to +125°C
−40°C to +125°C
300°C
125°C
1 The GATE pin has internal clamping circuits to prevent the GATE pin voltage
from exceeding the maximum ratings of a MOSFET with a gate to source
voltage (VGSMAX) = 20 V and internal process limits. Applying a voltage source
to this pin externally may cause irreversible damage.
ADM1272
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
THERMAL CHARACTERISTICS
Thermal performance is directly linked to printed circuit board
(PCB) design and operating environment. Careful attention to
PCB thermal design is required.
θJA is the natural convection junction to ambient thermal
resistance measured in a one cubic foot sealed enclosure. θJC is
the junction to case thermal resistance.
Table 5. Thermal Resistance
Package Type
CP-48-181
θJA θJC Unit
Still Air
50 0.5 °C/W
2 m/sec Air Flow
40 1
°C/W
1 The thermal resistance values are based on JEDEC 2S2P test conditions.
ESD CAUTION
Rev. 0 | Page 11 of 57
11 Page | ||
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| PDF Descargar | [ Datasheet ADM1272.PDF ] | |
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