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PDF MBM29F200BC-70 Data sheet ( Hoja de datos )
| Número de pieza | MBM29F200BC-70 | |
| Descripción | 2M (256K x 8/128K x 16) BIT FLASH MEMORY | |
| Fabricantes | Fujitsu | |
| Logotipo |  |
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FUJITSU SEMICONDUCTOR
DATA SHEET
DS05-20867-3E
FLASH MEMORY
CMOS
www.datasheet4u.com
2M (256K × 8/128K × 16) BIT
MBM29F200TC-55/-70/-90/MBM29F200BC-55/-70/-90
s FEATURES
• Single 5.0 V read, write, and erase
Minimizes system level power requirements
• Compatible with JEDEC-standard commands
Uses same software commands as E2PROMs
• Compatible with JEDEC-standard world-wide pinouts
48-pin TSOP (Package suffix: PFTN – Normal Bend Type, PFTR – Reversed Bend Type)
44-pin SOP (Package suffix: PF)
• Minimum 100,000 write/erase cycles
• High performance
55 ns maximum access time
• Sector erase architecture
One 16K byte, two 8K bytes, one 32K byte, and three 64K bytes.
Any combination of sectors can be concurrently erased. Also supports full chip erase.
• Boot Code Sector Architecture
T = Top sector
B = Bottom sector
• Embedded EraseTM Algorithms
Automatically pre-programs and erases the chip or any sector
• Embedded ProgramTM Algorithms
Automatically writes and verifies data at specified address
• Data Polling and Toggle Bit feature for detection of program or erase cycle completion
• Ready/Busy output (RY/BY)
Hardware method for detection of program or erase cycle completion
• Low Vcc write inhibit ≤ 3.2 V
• Erase Suspend/Resume
Suspends the erase operation to allow a read in another sector within the same device
• Hardware RESET pin
Resets internal state machine to the read mode
• Sector protection
Hardware method disables any combination of sectors from write or erase operations
• Temporary sector unprotection
Hardware method temporarily enables any combination of sectors from write on erase operations.
Embedded EraseTM and Embedded ProgramTM are trademarks of Advanced Micro Devices, Inc.
1 page  
MBM29F200TC-55/-70/-90/MBM29F200BC-55/-70/-90
s PRODUCT LINE UP
Part No.
www.dataOshredeet4ruin.cgomPart No.
VCC = 5.0 V ± 5%
VCC = 5.0 V ± 10%
Max. Address Access Time (ns)
Max. CE Access Time (ns)
Max. OE Access Time (ns)
s BLOCK DIAGRAM
MBM29F200TC/MBM29F200BC
-55 —
—
— -70 -90
55 70 90
55 70 90
30 30 35
VCC
VSS
WE
BYTE
RESET
CE
OE
RY/BY
Buffer
RY/BY
Erase Voltage
Generator
DQ0 to DQ15
Input/Output
Buffers
State
Control
Command
Register
Program Voltage
Generator
Chip Enable
Output Enable
Logic
STB Data Latch
A0 to A16
A-1
STB Y-Decoder
Low VCC Detector
Timer for
Program/Erase
Address
Latch
X-Decoder
Y-Gating
Cell Matrix
5
5 Page 
MBM29F200TC-55/-70/-90/MBM29F200BC-55/-70/-90
Table 4 .1 MBM29F200TC/BC Sector Protection Verify Autoselect Codes
Type
A12 to A16
A6
A1
A0 A-1*1
w w w . dMa taansuhfaecetut r4eur’.sc Co mode
X VIL VIL VIL VIL
Device Code
Byte
MBM29F200TC
Word
Byte
MBM29F200BC
Word
X
X
VIL
VIL VIL VIH
X
VIL
VIL VIL VIH
X
Sector Protection
Sector
Addresses
VIL
VIH
VIL
VIL
*1: A-1 is for Byte mode.
*2: Outputs 01H at protected sector addresses and outputs 00H at unprotected sector addresses.
Code
(HEX)
04H
51H
2251H
57H
2257H
01H*2
Table 4 .2 Expanded Autoselect Code Table
Type
Manufacturer’s Code
Code DQ15 DQ14 DQ13 DQ12 DQ11 DQ10
DQ9
DQ8
DQ
7
DQ
6
DQ
5
DQ
4
DQ
3
DQ
2
DQ
1
DQ
0
04H A-1/0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0
Device
Code
MBM29F200TC 51H
(B)
2251
A-1
0
HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z
0100010
0
0
1
1
0
0
1
1
0
0
0
0
0
0
1
1
(W) H
MBM29F200BC 57H
(B)
2257
A-1
0
HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z
0100010
0
0
1
1
0
0
1
1
0
0
1
1
1
1
1
1
(W) H
Sector Protection
01H A-1/0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
(B): Byte mode
(W): Word mode
Write
Device erasure and programming are accomplished via the command register. The contents of the register serve
as inputs to the internal state machine. The state machine outputs dictate the function of the device.
The command register itself does not occupy any addressable memory location. The register is a latch used to
store the commands, along with the address and data information needed to execute the command. The
command register is written by bringing WE to VIL, while CE is at VIL and OE is at VIH. Addresses are latched on
the falling edge of WE or CE, whichever happens later; while data is latched on the rising edge of WE or CE,
whichever happens first. Standard microprocessor write timings are used.
Refer to AC Write Characteristics and the Erase/Programming Waveforms for specific timing parameters.
Sector Protection
The MBM29F200TC/BC features hardware sector protection. This feature will disable both program and erase
operations in any number of sectors (0 through 6). The sector protection feature is enabled using programming
equipment at the user’s site. The device is shipped with all sectors unprotected.
11
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