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PDF MBM29F080A-55 Data sheet ( Hoja de datos )
| Número de pieza | MBM29F080A-55 | |
| Descripción | 8M (1M x 8) BIT FLASH MEMORY | |
| Fabricantes | Fujitsu | |
| Logotipo |  |
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FUJITSU SEMICONDUCTOR
DATA SHEET
FLASH MEMORY
CMOS
8M (1M × 8) BIT
DS05-20850-2E
MBM29F080A-55/-70/-90
s FEATURES
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Single 5.0 V read, write, and erase
Minimizes system level power requirements
Compatible with JEDEC-standard commands
Pinout and software compatible with single-power supply Flash
Superior inadvertent write protection
48-pin TSOP(I) (Package Suffix: PFTN-Normal Bend Type, PFTR-Reverse Bend Type)
40-pin TSOP(I) (Package Suffix: PTN-Normal Bend Type, PTR-Reversed Bend Type)
44-pin SOP (Package Suffix: PF)
Minimum 100,000 write/erase cycles
High performance
55 ns maximum access time
Sector erase architecture
Uniform sectors of 64 K bytes each
Any combination of sectors can be erased. Also supports full chip erase.
Embedded Erase™ Algorithms
Automatically pre-programs and erases the chip or any sector
Embedded Program™ Algorithms
Automatically programs and verifies data at specified address
Data Polling and Toggle Bit feature for detection of program or erase cycle completion
Ready/Busy output (RY/BY)
Hardware method for detection of program or erase cycle completion
Low VCC write inhibit ≤ 3.2 V
Hardware RESET pin
Resets internal state machine to the read mode
Erase Suspend/Resume
Supports reading or programming data to a sector not being erased
Sector group protection
Hardware method that disables any combination of sector groups from write or erase operation (a sector group
consists of 2 adjacent sectors of 64 K bytes each)
Temporary sector groups unprotection
Temporary sector unprotection via the RESET pin
Embedded Erase™, Embedded Program™ and ExpressFlash™ are trademarks of Advanced Micro Devices, Inc.
1 page  
s PRODUCT LINE UP
Part No.
Ordering Part No.
VCC = 5.0 V ±5%
VCC = 5.0 V ±10%
Max. Address Access Time (ns)
Max. CE Access Time (ns)
Max. OE Access Time (ns)
s BLOCK DIAGRAM
MBM29F080A-55/-70/-90
MBM29F080A
-55 —
—
— -70 -90
55 70 90
55 70 90
30 30 40
VCC
VSS
WE
RESET
CE
OE
RY/BY
Buffer
RY/BY
Erase Voltage
Generator
DQ0 to DQ7
Input/Output
Buffers
State
Control
Command
Register
Program Voltage
Generator
Chip Enable
Output Enable
Logic
STB Data Latch
A0 to A19
STB Y-Decoder
Low VCC Detector
Timer for
Program/Erase
Address
Latch
X-Decoder
Y-Gating
Cell Matrix
5
5 Page 
MBM29F080A-55/-70/-90
Type
Manufacture’s
Code
Table 3 MBM29F080A Sector Protection Verify Autoselect Codes
A17 to A19
A6
A1
A0
Code
(HEX)
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
X X X VIL VIL VIL 04H 0 0 0 0 0 1 0 0
Device Code
X X X VIL VIL VIH D5H 1 0 1 0 1 1 0 1
Sector Group
Protection
Sector Group
Addresses
VIL VIH VIL 01H*
0
0
0
0
0
0
0
1
* : Outputs 01H at protected sector addresses and outputs 00H at unprotected sector addresses.
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SA10
SA11
SA12
SA13
SA14
SA15
Table 4 Sector Address Table
A19 A18 A17 A16
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Address Range
000000H to 00FFFFH
010000H to 01FFFFH
020000H to 02FFFFH
030000H to 03FFFFH
040000H to 04FFFFH
050000H to 05FFFFH
060000H to 06FFFFH
070000H to 07FFFFH
080000H to 08FFFFH
090000H to 09FFFFH
0A0000H to 0AFFFFH
0B0000H to 0BFFFFH
0C0000H to 0CFFFFH
0D0000H to 0DFFFFH
0E0000H to 0EFFFFH
0F0000H to 0FFFFFH
SGA0
SGA1
SGA2
SGA3
SGA4
SGA5
SGA6
SGA7
Table 5 Sector Group Addresses
A19 A18 A17
000
001
010
011
100
101
110
111
Sectors
SA0 to SA1
SA2 to SA3
SA4 to SA5
SA6 to SA7
SA8 to SA9
SA10 to SA11
SA12 to SA13
SA14 to SA15
11
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