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PDF MBM29DL800TA-70 Data sheet ( Hoja de datos )
| Número de pieza | MBM29DL800TA-70 | |
| Descripción | 8M (1M x 8/512K x 16) BIT FLASH MEMORY | |
| Fabricantes | Fujitsu | |
| Logotipo |  |
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FUJITSU SEMICONDUCTOR
DATA SHEET
DS05-20860-3E
FLASH MEMORY
CMOS
8M (1M × 8/512K × 16) BIT
MBM29DL800TA-70/-90/-12/MBM29DL800BA-70/-90/-12
s FEATURES
• Single 3.0 V read, program, and erase
Minimizes system level power requirements
• Simultaneous operations
Read-while-Erase or Read-while-Program
• Compatible with JEDEC-standard commands
Uses same software commands as E2PROMs
• Compatible with JEDEC-standard world-wide pinouts (Pin compatible with MBM29LV800TA/BA)
48-pin TSOP(I) (Package suffix: PFTN – Normal Bend Type, PFTR – Reversed Bend Type)
48-ball FBGA (Package suffix: PBT)
• Minimum 100,000 program/erase cycles
• High performance
70 ns maximum access time
• Sector erase architecture
Two 16K byte, four 8K bytes, two 32K byte, and fourteen 64K bytes.
Any combination of sectors can be concurrently erased. Also supports full chip erase.
• Boot Code Sector Architecture
T = Top sector
B = Bottom sector
• Embedded EraseTM Algorithms
Automatically pre-programs and erases the chip or any sector
• Embedded ProgramTM Algorithms
Automatically writes and verifies data at specified address
• Data Polling and Toggle Bit feature for detection of program or erase cycle completion
• Ready/Busy output (RY/BY)
Hardware method for detection of program or erase cycle completion
• Automatic sleep mode
When addresses remain stable, automatically switch themselves to low power mode.
• Low VCC write inhibit ≤ 2.5 V
• Erase Suspend/Resume
Suspends the erase operation to allow a read in another sector within the same device
(Continued)
Embedded EraseTM and Embedded ProgramTM are trademarks of Advanced Micro Devices, Inc.
1 page  
MBM29DL800TA-70/-90/-12/MBM29DL800BA-70/-90/-12
s PRODUCT LINE UP
Part No.
Ordering Part No.
VCC = 3.3 V
+0.3 V
–0.3 V
VCC = 3.0 V
+0.6 V
–0.3 V
Max. Address Access Time (ns)
Max. CE Access Time (ns)
Max. OE Access Time (ns)
MBM29DL800TA/MBM29DL800BA
-70 — —
— -90 -12
70 90 120
70 90 120
30 35 50
s BLOCK DIAGRAM
RY/BY
Buffer
RY/BY
V CC
V SS Erase Voltage
Generator
DQ 0 to DQ 15
Input/Output
Buffers
WE
BYTE
RESET
CE
OE
State
Control
Command
Register
Program Voltage
Generator
Chip Enable
Output Enable
STB
Data Latch
Logic
A0 to A18
A-1
STB Y-Decoder
Low V CC Detector
Timer for
Program/Erase
Address
Latch
X-Decoder
Y-Gating
Cell Matrix
5
5 Page 
MBM29DL800TA-70/-90/-12/MBM29DL800BA-70/-90/-12
s FUNCTIONAL DESCRIPTION
Simultaneous Operation
MBM29DL800TA/BA have feature, which is capability of reading data from one bank of memory while a program
or erase operation is in progress in the other bank of memory (simultaneous operation), in addition to the
conventional features (read, program, erase, erase-suspend read, and erase-suspend program). The bank
selection can be selected by bank address (A16 to A18) with zero latency.
The MBM29DL800TA/BA have two banks which contain Bank 1 (16KB, 32KB, 8KB, 8KB, 8KB, 8KB, 32KB, and
16KB) and Bank 2 (64KB × fourteen sectors).
The simultaneous operation can not execute multi-function mode in the same bank. Table 4 shows combination
to be possible for simultaneous operation.
Case
1
2
3
4
5
6
7
Table 4 Simultaneous Operation
Bank 1 Status
Read mode
Read mode
Read mode
Read mode
Autoselect mode
Program mode
Erase mode *
Bank 2 Status
Read mode
Autoselect mode
Program mode
Erase mode *
Read mode
Read mode
Read mode
*: An erase operation may also be supended to read from or program to a sector not being erased.
Read Mode
The MBM29DL800TA/BA have two control functions which must be satisfied in order to obtain data at the outputs.
CE is the power control and should be used for a device selection. OE is the output control and should be used
to gate data to the output pins if a device is selected.
Address access time (tACC) is equal to the delay from stable addresses to valid output data. The chip enable
access time (tCE) is the delay from stable addresses and stable CE to valid data at the output pins. The output
enable access time is the delay from the falling edge of OE to valid data at the output pins. (Assuming the
addresses have been stable for at least tACC-tOE time.) When reading out a data without changing addresses after
power-up, it is necessary to input hardware reset or to change CE pin from “H” or “L”
Standby Mode
There are two ways to implement the standby mode on the MBM29DL800TA/BA devices, one using both the
CE and RESET pins; the other via the RESET pin only.
When using both pins, a CMOS standby mode is achieved with CE and RESET inputs both held at VCC ± 0.3 V.
Under this condition the current consumed is less than 5 µA max. During Embedded Algorithm operation, VCC
active current (ICC2) is required even CE = “H”. The device can be read with standard access time (tCE) from either
of these standby modes.
When using the RESET pin only, a CMOS standby mode is achieved with RESET input held at VSS ± 0.3 V (CE
= “H” or “L”). Under this condition the current is consumed is less than 5 µA max. Once the RESET pin is taken
high, the device requires tRH of wake up time before outputs are valid for read access.
In the standby mode the outputs are in the high impedance state, independent of the OE input.
11
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| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet MBM29DL800TA-70.PDF ] | |
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