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PDF MBM29DL400TC-70 Data sheet ( Hoja de datos )
| Número de pieza | MBM29DL400TC-70 | |
| Descripción | 4M (512K x 8/256K x 16) BIT | |
| Fabricantes | Fujitsu | |
| Logotipo |  |
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FUJITSU SEMICONDUCTOR
DATA SHEET
DS05-20866-2E
FLASH MEMORY
CMOS
4M (512K × 8/256K × 16) BIT
MBM29DL400TC-55/-70/-90/-12/MBM29DL400BC-55/-70/-90/-12
s FEATURES
• Single 3.0 V read, program, and erase
Minimizes system level power requirements
• Simultaneous operations
Read-while-Erase or Read-while-Program
• Compatible with JEDEC-standard commands
Uses same software commands as E2PROMs
• Compatible with JEDEC-standard world-wide pinouts (Pin compatible with MBM29LV400TC/BC)
48-pin TSOP(I) (Package suffix: PFTN – Normal Bend Type, PFTR – Reversed Bend Type)
• Minimum 100,000 program/erase cycles
• High performance
55 ns maximum access time
• Sector erase architecture
Two 16K byte, four 8K bytes, two 32K byte, and six 64K bytes.
Any combination of sectors can be concurrently erased. Also supports full chip erase.
• Boot Code Sector Architecture
T = Top sector
B = Bottom sector
• Embedded EraseTM Algorithms
Automatically pre-programs and erases the chip or any sector
• Embedded ProgramTM Algorithms
Automatically writes and verifies data at specified address
• Data Polling and Toggle Bit feature for detection of program or erase cycle completion
• Ready/Busy output (RY/BY)
Hardware method for detection of program or erase cycle completion
• Automatic sleep mode
When addresses remain stable, automatically switch themselves to low power mode.
• Low VCC write inhibit ≤ 2.5 V
• Erase Suspend/Resume
Suspends the erase operation to allow a read in another sector within the same device
(Continued)
Embedded EraseTM and Embedded ProgramTM are trademarks of Advanced Micro Devices, Inc.
1 page  
MBM29DL400TC-55/-70/-90/-12/MBM29DL400BC-55/-70/-90/-12
s PRODUCT LINE UP
Part No.
Ordering Part No.
VCC = 3.3 V
+0.3 V
–0.3 V
VCC = 3.0 V
+0.6 V
–0.3 V
Max. Address Access Time (ns)
Max. CE Access Time (ns)
Max. OE Access Time (ns)
s BLOCK DIAGRAM
MBM29DL400TC/MBM29DL400BC
-55 -70
—
—
— — -90 -12
55 70 90 120
55 70 90 120
30 30 35 50
V CC
V SS
A0 to A17
(A-1)
Bank 2 Address
RESET
WE
CE
OE
BYTE
DQ 0 to DQ 15
State
Control
Command
Register
RY/BY
Status
Bank 1 Address
Cell Matrix
(Bank 2)
X-Decoder
X-Decoder
Cell Matrix
(Bank 1)
.
DQ 0 to DQ 15
5
5 Page 
MBM29DL400TC-55/-70/-90/-12/MBM29DL400BC-55/-70/-90/-12
Automatic Sleep Mode
There is a function called automatic sleep mode to restrain power consumption during read-out of
MBM29DL400TC/BC data. This mode can be used effectively with an application requested low power
consumption such as handy terminals.
To activate this mode, MBM29DL400TC/BC automatically switch themselves to low power mode when
MBM29DL400TC/BC addresses remain stably during access fine of 150 ns. It is not necessary to control CE,
WE, and OE on the mode. Under the mode, the current consumed is typically 1 µA (CMOS Level).
During simultaneous operation, VCC active current (ICC2) is required.
Since the data are latched during this mode, the data are read-out continuously. If the addresses are changed,
the mode is canceled automatically and MBM29DL400TC/BC read-out the data for changed addresses.
Output Disable
With the OE input at a logic high level (VIH), output from the devices are disabled. This will cause the output pins
to be in a high impedance state.
Autoselect
The autoselect mode allows the reading out of a binary code from the devices and will identify its manufacturer
and type. This mode is intended for use by programming equipment for the purpose of automatically matching
the devices to be programmed with its corresponding programming algorithm. This mode is functional over the
entire temperature range of the devices.
To activate this mode, the programming equipment must force VID (11.5 V to 12.5 V) on address pin A9. Two
identifier bytes may then be sequenced from the devices outputs by toggling address A0 from VIL to VIH. All
addresses are DON’T CARES except A0, A1, and A6 (A-1). (See Tables 2 and 3.)
The manufacturer and device codes may also be read via the command register, for instances when the
MBM29DL400TC/BC are erased or programmed in a system without access to high voltage on the A9 pin. The
command sequence is illustrated in Table 8. (Refer to Autoselect Command section.)
Word 0 (A0 = VIL) represents the manufacturer’s code (Fujitsu = 04H) and word 1 (A0 = VIH) represents the device
identifier code (MBM29DL400TC = 0CH and MBM29DL400BC = 0FH for ×8 mode; MBM29DL400TC = 220CH
and MBM29DL400BC = 220FH for ×16 mode). These two bytes/words are given in the tables 5.1 and 5.2. All
identifiers for manufactures and device will exhibit odd parity with DQ7 defined as the parity bit. In order to read
the proper device codes when executing the autoselect, A1 must be VIL. (See Tables 5.1 and 5.2.)
In case of applying VID on A9, since both Bank 1 and Bank 2 enters Autoselect mode, the simultenous operation
can not be executed.
11
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| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet MBM29DL400TC-70.PDF ] | |
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