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M5M44405CJ-5S fiches techniques PDF

Mitsubishi - EDO 4M-Bit DRAM

Numéro de référence M5M44405CJ-5S
Description EDO 4M-Bit DRAM
Fabricant Mitsubishi 
Logo Mitsubishi 





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M5M44405CJ-5S fiche technique
MITMSIUTSBUISBHISI LHSI ILsSIs
M5M44405CJM,T5MP4-4540,-56C,J-,T7P,--55,-S6,,-7-,6-5SS,,--67SS,-7S
EDOED(OHY( PHEYRPEPRAGPAEGMEOMDOED) E41)9441390443-0B4IT-B(IT10(4180547865-7W6O-WRODRBDYB4Y-B4IT-B)ITDY) NDAYNMAICMRICARMAM
DESCRIPTION
This is a family of 1048576-word by 4-bit dynamic RAMs, fabricated
with the high performance CMOS process,and is ideal for large-
capacity memory systems where high speed, low power dissipation,
and low costs are essential.
The use of quadruple-layer polysilicon process combined with
silicide technology and a single-transistor dynamic storage stacked
capacitor cell provide high circuit density at reduced costs.
Multiplexed address inputs permit both a reduction in pins and an
increase in system densities.
Self or extended refresh current is low enough for battery back-up
application.
PIN CONFIGURATION (TOP VIEW)
DQ1 1
DQ2 2
W3
RAS 4
A9 5
26 VSS
25 DQ4
24 DQ3
23 CAS
22 OE
FEATURES
Type name
RAS
access
time
(max.ns)
CAS
access
time
(max.ns)
Address
access
time
(max.ns)
OE
access
time
(max.ns)
Cycle
time
(min.ns)
Power
dissipa-
tion
(typ.mW)
M5M44405CXX-5,-5S 50 13 25 13
90 500
M5M44405CXX-6,-6S 60 15 30 15 110 400
M5M44405CXX-7,-7S 70 20 35 20 130 350
XX=J,TP
Standard 26 pin SOJ, 26 pin TSOP(II)
Single 5V±10%supply
Low stand-by power dissipation
CMOS lnput level
5.5mW (Max) *
CMOS lnput level
550µW (Max)
Low operating power dissipation
M5M44405Cxx-5,-5S
687.5mW (Max)
M5M44405Cxx-6,-6S
550.0mW (Max)
M5M44405Cxx-7,-7S
467.5mW (Max)
Self refresh capabiility *
Self refresh current
120µA(max)
Extended refresh capability *
Extended refresh current
120µA(max)
Hyper-page mode (1024-bit random access), Read-modify- write,
RAS-only refresh CAS before RAS refresh, Hidden refresh, CBR
self refresh(-5S,-6S,-7S) capabilities
Early-write mode and OE and W to control output buffer impedance
All inputs, output TTL compatible and low capacitance
1024 refresh cycles every 16.4ms (A0~A9)
1024refresh cycle every 128ms (A0~A9) *
4-bit parallel test mode capability
* : Applicable to self refresh version (M5M44405CJ,TP-5S,-6S,-7S
: option) only
APPLICATION
Main memory unit for computers, Microcomputer memory, Refresh
memory for CRT, Frame Buffer memory for CRT
PIN DESCRIPTION
Pin name
Function
A0~A9
Address Inputs
DQ1~DQ4 Data Inputs / Outputs
RAS
Row Address Strobe Input
CAS
Column Address Strobe Input
W Write Control Input
OE Output Enable Input
Vcc Power Supply (+5V)
1 Vss
Ground (0V)
M5M44405CJ,TP-5,-5S:Under development
A0 9
A1 10
A2 11
A3 12
VCC 13
18 A8
17 A7
16 A6
15 A5
14 A4
Outline 26P0J (300mil SOJ)
DQ1 1
DQ2 2
W3
RAS 4
A9 5
26 VSS
25 DQ4
24 DQ3
23 CAS
22 OE
A0 9
A1 10
A2 11
A3 12
VCC 13
18 A8
17 A7
16 A6
15 A5
14 A4
Outline 26P3Z-E (300mil TSOP)

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