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M5M4V4405CJ-7 fiches techniques PDF

Mitsubishi - EDO (HYPER PAGE MODE) 4M-BIT(1048576-WORD BY 4-BIT) DYNAMIC RAM

Numéro de référence M5M4V4405CJ-7
Description EDO (HYPER PAGE MODE) 4M-BIT(1048576-WORD BY 4-BIT) DYNAMIC RAM
Fabricant Mitsubishi 
Logo Mitsubishi 





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M5M4V4405CJ-7 fiche technique
MITSMUIBTSISUHBI ISLHSIsLSIs
M5M4V4405MC5JM,4TVP44-065,C-J7,T,-P6-6S,-7,,--76SS,-7S
EDOE(DHOYP(HEYRPPEARGPEAMGOEDMEO) D41E9)44310944-3B0I4T-B(1I0T4(180547865-W76O-WRDORBDY B4-YB4IT-B) DITY)NDAYMNIACMRICAMRAM
DESCRIPTION
This is a family of 1048576-word by 4-bit dynamic RAMS,
fabricated with the high performance CMOS process,and is ideal
for large-capacity memory systems where high speed, low power
dissipation , and low costs are essential.
The use of quadruple-layer polysilicon process combined with
silicide technology and a single-transistor dynamic storage stacked
capacitor cell provide high circuit density at reduced costs.
Multiplexed address inputs permit both a reduction in pins and an
increase in system densities.
Self or extended refresh current is low enough for battery
back-up application.
PIN CONFIGURATION (TOP VIEW)
DQ1 1
DQ2 2
W3
RAS 4
A9 5
26 VSS
25 DQ4
24 DQ3
23 CAS
22 OE
FEATURES
Type name
RAS CAS Address OE
access access access access
time time time time
Cycle
Power
dissipa-
time tion
(max.ns) (max.ns) (max.ns) (max.ns) (min.ns) (typ.mW)
M5M4V4405CXX-6, -6S 60 15 30 15 110 264
M5M4V4405CXX-7, -7S 70 20 35 20 130 231
XX=J, TP
Standard 26 pin SOJ, 26 pin TSOP(II)
Single 3.3V±0.3V supply
Low stand-by power dissipation
CMOS lnput level .................................................1.8mW(Max)*
CMOS lnput level ................................................180µW(Max)
Low operating power dissipation
M5M4V4405Cxx-6, -6S .....................................288.0mW (Max)
M5M4V4405Cxx-7, -7S ....................................252.0mW (Max)
Self refresh capabiility*
Self refresh current ..............................................100µA(max)
Extended refresh capability*
Extended refresh current ....................................100µA(max)
Hyper-page mode (1024-bit random access), Read-modify- write,
RAS-only refresh CAS before RAS refresh, Hidden refresh, CBR
self refresh(-6S,-7S) capabilities.
Early-write mode and OE and W to control output buffer impedance
1024 refresh cycles every 16.4ms (A0~A9)
1024refresh cycle every128ms (A0~A9)*
*: Applicable to self refresh version (M5M4V4405Cxx-6S,-7S:
option) only
APPLICATION
Lap top personal computer,Solid state disc, Microcomputer
memory, Refresh memory for CRT
A0 9
A1 10
A2 11
A3 12
VCC 13
18 A8
17 A7
16 A6
15 A5
14 A4
Outline 26P0J (300mil SOJ)
DQ1 1
DQ2 2
W3
RAS 4
A9 5
26 VSS
25 DQ4
24 DQ3
23 CAS
22 OE
A0 9
A1 10
A2 11
A3 12
VCC 13
18 A8
17 A7
16 A6
15 A5
14 A4
Outline 26P3Z-E (300mil TSOP)
PIN DESCRIPTION
Pin name
A0~A9
DQ1~DQ4
RAS
CAS
W
OE
VCC
VSS
Function
Address inputs
Data inputs / outputs
Row address strobe input
Column address strobe input
Write control input
Output enable input
Power supply (+3.3V)
Ground (0V)
1

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