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M5M4V4265CJ-6S fiches techniques PDF

Mitsubishi - EDO 4M-Bit DRAM

Numéro de référence M5M4V4265CJ-6S
Description EDO 4M-Bit DRAM
Fabricant Mitsubishi 
Logo Mitsubishi 





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M5M4V4265CJ-6S fiche technique
MITMSUITBSIUSHBISLHSIIsLSIs
M5M4V4265CJM,5TMP4V-452,6-56C,J-,7TP,--55,-S6,,--76,-5SS,,--67SS,-7S
EDOED(HOY(PHEYRPPEARGPEA)GMEO) DMEO4D1E9431094-3B0I4T-B(2IT62(124642-1W44O-WRDORBDY 1B6Y-B1I6T-)BDITY)NDAYMNIACMRICAMRAM
DESCRIPTION
This is a family of 262144-word by 16-bit dynamic RAMs with EDO
mode fuction, fabricated with the high performance CMOS
process, and is ideal for the buffer memory systems of personal
computer graphics and HDD where high speed, low power
dissipation, and low costs are essential. The use of double-layer
metalization process technology and a single-transistor dynamic
storage stacked capacitor cell provide high circuit density at
reduced costs. The lower supply (3.3V) operation, due to the
optimization of transistor structure, provides low power dissipation
while maintaining high speed operation. Multiplexed address inputs
permit both a reduction in pins and an increase in system
densities. Self or extended refresh current is low enough for
battery back-up application. This device has 2CAS and 1W
terminals with a refresh cycle of 512 cycles every 8.2ms.
FEATURES
Type name
RAS
CAS Address
access access access
time time time
OE Cycle
access
time
time
Power
dissipa-
tion
(max.ns) (max.ns) (max.ns) (max.ns) (min.ns) (typ.mW)
M5M4V4265CXX-5,-5S 50
13
25 13
90 408
M5M4V4265CXX-6,-6S 60 15 30 15 110 363
M5M4V4265CXX-7,-7S 70 20 35 20 130 333
XX=TP,J
Standard 40 pin SOJ, 44 pin TSOP (II)
Single 3.3±0.3V supply
Low stand-by power dissipation
CMOS Input level
1.8mW (Max)
CMOS Input level
360µW (Max) *
Operating power dissipation
M5M4V4265CXX-5,-5S
486mW (Max)
M5M4V4265CXX-6,-6S
432mW (Max)
M5M4V4265CXX-7,-7S
396mW (Max)
Self refresh capability *
Self refresh current
100µA (Max)
Extended refresh capability
Extended refresh current
100µA (Max)
EDO mode (512-column random access), Read-modify-write, RAS-
only refresh, CAS before RAS refresh, Hidden refresh capabilities.
Early-write mode, OE and W to control output buffer impedance
512 refresh cycles every 8.2ms (A0~A8)
512 refresh cycles every 128ms (A0~A8) *
Byte or word control for Read/Write operation (2CAS, 1W type)
* : Applicable to self refresh version (M5M4V4265CJ,TP-5S,-6S,
-7S : option) only
APPLICATION
Microcomputer memory, Refresh memory for CRT, Frame buffer
memory for CRT
PIN DESCRIPTION
Pin name
A0~A8
DQ1~DQ16
RAS
LCAS
Function
Address inputs
Data inputs / outputs
Row address strobe input
Lower byte control
column address strobe input
UCAS
Upper byte control
column address strobe input
W Write control input
OE Output enable input
VCC Power supply (+3.3V)
VSS Ground (0V)
1
M5M4V4265CJ,TP-5,-5S:under development
PIN CONFIGURATION (TOP VIEW)
(3.3V)VCC 1
DQ1 2
DQ2 3
DQ3 4
DQ4 5
(3.3V)VCC 6
DQ5 7
DQ6 8
DQ7 9
DQ8 10
NC 11
NC 12
W 13
RAS 14
NC 15
A0 16
A1 17
A2 18
A3 19
(3.3V)VCC 20
40 VSS(0V)
39 DQ16
38 DQ15
37 DQ14
36 DQ13
35 VSS(0V)
34 DQ12
33 DQ11
32 DQ10
31 DQ9
30 NC
29 LCAS
28 UCAS
27 OE
26 A8
25 A7
24 A6
23 A5
22 A4
21 VSS(0V)
Outline 40P0K (400mil SOJ)
(3.3V)VCC 1
DQ1 2
DQ2 3
DQ3 4
DQ4 5
(3.3V)VCC 6
DQ5 7
DQ6 8
DQ7 9
DQ8 10
44 VSS(0V)
43 DQ16
42 DQ15
41 DQ14
40 DQ13
39 VSS(0V)
38 DQ12
37 DQ11
36 DQ10
35 DQ9
NC 13
NC 14
W 15
RAS 16
NC 17
A0 18
A1 19
A2 20
A3 21
(3.3V)VCC 22
32 NC
31 LCAS
30 UCAS
29 OE
28 A8
27 A7
26 A6
25 A5
24 A4
23 VSS(0V)
Outline 44P3W-R (400mil TSOP Nomal Bend)
NC : NO CONNECTION

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