|
|
PDF M5M4256L-15 Data sheet ( Hoja de datos )
| Número de pieza | M5M4256L-15 | |
| Descripción | 256K-Bit DRAM | |
| Fabricantes | Mitsubishi | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de M5M4256L-15 (archivo pdf) en la parte inferior de esta página. Total 15 Páginas | ||
|
No Preview Available !
MITSUBISHI LSls
M5M4256L-12, -15, -20
262 144-BIT (262 144-WORDBY I-BIT) DYNAMIC RAM
DESCRIPTION
This is a family of 262 144-word by l-bit dynamic RAMs,
fabricated with the high performance N-channel silicon gate
MOS process, and is ideal for large-capacity memory
systems where high speed, low power dissipation, and low
costs are essential. The use of double-layer polysilicon
process combined with silicide technology and a single-
transistor dynamic storage cell provide high circuit density
at reduced costs, and the use of dynamic circuitry including
sense amplifiers assures low power dissipation. Multiplexed
address inputs permit both a reduction in pins to the 16 pin
zigzag inline package configuration and an increase in
system densities. In addition to the RAS only refresh mode,
the Hidden refresh mode and CAS before RAS refresh
mode are available.
FEATURES
Type name
Access tIme
(max)
(ns)
Cycle time
(min)
(ns)
Power dissipation
(typ)
(mW)
M5M4256L-12
120
230
260
M5M4256L-15
150
260
230
M5M4256L- 20
200
330
190
• 16 pin zigzag inllne package
• Single 5V±10% supply
• Low standby power dissipation:
25mW (max)
• Low operating power dissipation:
M5M4256L-12 ........... 360mW (max)
M5M4256L·15 ........... 330mW (max)
M5M4256L-20 . . . . . . . . . . . 275mW (max)
• Unlatched output enables two-dimensional chip selec·
tion and extended page boundary.
PIN CONFIGURATION (TOP VIEW)
ADDRESS INPUT
COLUMN ADDRESS
STROBE INPUT
ADDRESS INPUT
A6 i1
CAS
~J
As -+ §J
[~ - Q DATA OUTPUT
ri
L_
VSS (OV)
'''"'~ { gWRITE CONTROL
INPUT
INPUTS
fJ '" ~~:O:~?~:J~Vi :!: [§ +-D DATA INPUT
[1~Ao
~]
:!: ~8
.... L_
+-
RAS
+- A Z ADDRESS" INPUT
A, -+ (,] r
ff~ Vee (5V)
AT -+ 1)}
A4 -+ (51
~:4 +- As } ADDRESS
[(6 +- A3 INPUTS
Outline 16P5A
• Early-write operation gives common I/O capability
• Read-modify·write, RAS-only·refresh, Page·mode capa-
bilities
• CAS before RAS refresh mode capability
• All input terminals have low input capacitance and are
directly TTL-compatible
• Output is three-state and directly TTL-compatible
• 256 refresh cycles every 4ms. Pin 1 is not needed for
refresh.
• CAS controlled output allows hidden refresh
APPLICATION
• Main memory unit for computers
• Microcomputer memory
BLOCK DIAGRAM
, DATA INPUT
WRITE CONTROL
INPUT
D 6 }--------------------------,
w 7r-----------------~---f~--------~--~
INPUT
LATCH
I
~VCc(5V)
I
ADDRESS
INPUTS
a: a:
A,
1' ' "'Az
32K
MEMORY
ARRAY
w
0
u0w
32K
MEMORY
ARRAY
32K
MEMORY
ARRAY
w
0
u0
W
32K
MEMORY
ARRAY
f-
A3
0 0 u:aJ: I
U
..J
A4
COLUMN
DECODER
a0:
DATA
As
fz- OUTPUT
u0
JAT
32K
MEMORY
ARRAY
S
0a:
32K
MEMORY
ARRAY
32K
MEMORY
ARRAY
S
-a0:
32K
MEMORY
ARRAY
§;
' - - - - L - - -_ _ _ _
2-140
• MITSUBISHI
.... ELECTRIC
1 page  
MITSUBISHI LSls
M5M4256L-12, -15, -20
262 i44·BIT (262 i44·WORD BY 1.BIT) DYNAMIC RAM
TIMING REQUIREMENTS (For Read, Write, Read-Modify-Write, Refresh,and Page-Mode Cycle)
(Ta =O-10"C. Vcc=SV.!: 10%. Vss=OV. unlessotherwisenoted;Seenotes5,6and7)
Symbol
Parameter
leAF
I WIAASH)
I wIAASL)
tW(CASL)
t WICASH)
Ih IAAS-CAS)
Ih (CAS-RAS)
td (CAS-RAS)
Id I RAS-CAS)
Isu (RA-RAS)
Isu ICA-CAS)
I h (AAS-RA)
I h ICAS-CA)
t h IAAS-CA)
I THL
I TLH
Refresh cycle time
RAS high pulse width
RAS low pulse width
CAS low pu Ise width
CAS high pulse width
CAS hold time after RAS
RAS hold time after 00
Delay time, <:AS to RAS
Delay time, RAS to CAS
Row address setup time before ~
Column address setup time before CAS
Row address hold time after RA."S
Column address hold time after CAS
Column address hold time after AAS
Transition time
(Note81
(Note 9)
INote 101
Alternative
Symbol
IAEF
lAP
I AAS
ICAS·
ICPN
ICSH
I ASH
I CAP
IRCO
IASR
IASC
I AAH
ICAH
IAA
IT
limits
M5M4256L-12 M5M4256L-15 M5M4256L-20
Min Max Min Max Min Max
44
4
100 100 120
120 10000 150 10000 200 10000
60 75 100
30 35 40
120 150 200
60 75 100
30 30 40
25
60 25
75 30
100
000
0 -5 -5
15 20 25
20 25 35
80 100 135
3 50 3 50 3 50
Note 5
6
1Q'
An initial pause of 500~s is required after power·u~ followed by any eight RAS or RAS/CAS cycles before proper device operation is achieved.
The switching characteristics are defined as t THL = t TLH = 5ns.
Reference levels of input signals are VIH min. and V1l max. Reference levels for transition time are also between VIH and Vil-
Except for page· mode.
td (CAS-RAS) requirement is applicable for all RAS/CAS cycles
Operation within the t d (RAS-CAS) max. limit insures that ta (RAS) max can be met. t d (RAS-CAS)maX is specified reference point only;if
td (RAS-CAS) is greater than the specified t d (RAS-CAS) max limit. then access time is controlled exclusively by ta (CAS).
Id (AAS-CAs)mon = I h (AAS-RA)mon + 21 THL It TkH) + I su iCA-CAS)mln_
Unit
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SWITCHING CHARACTERISTICS (T. =0-70'C, Vcc=5V ± 10%, VSS=OV. unless otherwISe noted)
Read Cycle
Symbol
Parameter
Alternative
Symbol
limits
M5M4256L-12 M5M4256L-15 M5M4256L-20
Min Max Min Max Min Max
leA
Isu (A-CAS)
Ih(CAS-A)
Ihl RAS-R)
Id.ls ICAS)
ta (CAS)
Read cycle time
Read setup time before CAS
Read hold time after CAS
Read hold time after RAS
Output disable time
CAS access time
(Note 11)
INote 111
INote 121
(Note 131
I RC
lACS
I ACH
IARH
IOFF
I CAC
230 260 330
aa0
aaa
20 20 25
0 35
a 40
0 50
60 75 100
I'IRAS)
RAS access time
(Note 141
tRAC
120 150 200
Note 11
12
13
14:
Either t h (RAS- A) or t h (CAS- R) must be satisfied for a read cycle.
td IS (CAS)ma x defines the time at which the output achieves the open circuit condition and is not reference to V OH or VOL
This is the value when td (RAS-CAS)~ t d {RAS-CAS)max. Test conditions; Load = 2T TL. Cl = l00pF
This is the value when t d (RAS-CAS)< td(RAS-CAS)max. When t d (RAS-CAS)~ t d (RAS-CAS)max. ta (RA'S) Will increase by the amount that
t d (AAS-CAS) ,exceeds the value shown Test conditions. Load = 2T TL Cl = 100pF
Write Cycle
Unit
ns
ns
ns
ns
ns
ns
ns
Symbol
Parameter
lew
Isu (W-CAS)
Ih (CAS-W)
Ih (RAS-W)
IhIW-AAS)
Ih IW-CAS)
Iw(w)
Isu (c-CAS)
Ih (CAS-O)
I h (RAS-O)
Write cycle time
Write setup time before CAS
Write hold time after CAS
Write hold time after RAS
RAS"hold time after write
CAS hold time after write
Write pulse width
Data·in setup time before CAS
Data·in hold time after CAS
Data-in hold time after FfAS
(Note 17)
Alternative
Symbol
I RC
IWCS
IWCH
IWCR
I RWL
ICWL
Iwp
lOS
IOH
IOHA
Li.mits
M5M4256L-12 M5M4256L-15 M5M4256L-20
Min Max Min Max Min Max
230 260 330
5 -10 -10
40 45 55
100 120 155
40 45 55
40 45 55
40 45 55
aaa
30 35 40
90 110 140
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2-144
• MITSUBISHI
~ELECTRIC
5 Page 
MITSUBISHI LSls
M5M4256L-12, -15, -20
262 144-BIT (262 144-WORD BY I-BIT) DYNAMIC RAM
TYPICAL CHARACTERISTICS
NORMALIZED ACCESS TIME
VS.SUPPlY VOLTAGE
1.3
U;
!'5" 1.2
:J
w
:;;
;::::
1.1
U1
U1
W
uu 1.0
<t
0
w
N
0.9
::i
:<;;t
cr:
0z
o.a
\ Ta ~2S'C
\
I'"1""-I'--..
....... r--
0.7
4.0 5.0 6.0
SUPPLY VOLTAGE Vee (V)
NORMALIZED ACCESS TIME
VS. AMBIENT TEMPERATURE
1.3
Vl
!'"5 1.2
:J
w
:;;
;::::
1.1
~
uu 1.0
<t
0
w
N
0.9
::i
<t
:;;
cr: o.a
0z
vec~s.o)
V
./
V
;'
[/
[7
20 40 60 ao 100
AMBIENT TEMPERATURE Ta ("C)
ACCESS TIME VS. LOAD
CAPACITANCE
25 1 ,I,
Vee=4.SV
-;; 20 I-- Ta =2S'C
-S
Vl
!'5" 15
:J
<l 10
w
~
f-
U1
U1
UJ
uU
<t a
VV
/""V
"
;'
-5 100 zoo 300 400 500 600
LOAD CAPACITANCE CL (pF)
OPERATING CURRENT
VS. SUPPLY VOLTAGE
ao
Ta 1= ZS'C [
S<t 70 ~teR=Z60ns
1
QI
-0 60
f-
Z
w
cr: 50
cr:
::J
U
CJ
~
40
f-
<t
cr:
VV
UJ
"-
30 ,,/
0
./
./"
./'"
20
4.0
5.0
6.0
SUPPLY VOLT AGE Vee (V)
OPERATING CURRENT
VS. AMBIENT TEMPERATURE
<t
E
oo SO~--+---+---+----+---+-~
f-
Z
UJ
cr:
40~--+---+---+---+---+-~
cr:
::J
U
CJ 30~--+---+---+---+---+-~
Z
f-
<t
cr:
UJ
ZO~~+---+---+---+---+---1
"o-
1 0L_-"zoo--..I..0--Z.,L0--4..LO"'--6..L0"'--a.,L0"'-.......J,0 0
AMBIENT TEMPERATURE Ta ('C)
OPERATING CURRENT
VS. CYCLE RATE
60 I
Vee=S.SV
<t
E
50 I-Ta =ZS'C
Qo
40
/
LV
V.
f-
~
cr:
30
cr:
::J
/
V
U
/CJ ZO
Z
Vf<-t
cr:
w
"o-
10
/
/
o Z4
CYCLE RATE l/t eR (MHz)
2-150
• MITSUBISHI
.... ELECTRIC
11 Page | ||
| Páginas | Total 15 Páginas | |
| PDF Descargar | [ Datasheet M5M4256L-15.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| M5M4256L-12 | 256K-Bit DRAM | Mitsubishi |
| M5M4256L-15 | 256K-Bit DRAM | Mitsubishi |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |