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Numéro de référence | M5M4257S-15 | ||
Description | 256K-Bit DRAM | ||
Fabricant | Mitsubishi | ||
Logo | |||
MITSUBISHI LSls
MSM42S7S·12, -15, -20
262 i44-BIT (262 i44-WORD BY i-BIT) DYNAMIC RAM
DESCRIPTION
This is a family of 262 l44-word by l-bit dynamic RAMs,
fabricated with the high performance N-channel silicon gate
MOS process, and is ideal for large-capacity memory
systems where high speed, low power dissipation, and low
costs are essential. The use of double-layer polysilicon
process combined with silicide technology and a single-
transistor dynamic storage cell provide high circuit density
at reduced costs, and the use of dynamic circuitry including
sense amplifiers assures low power dissipation. Multiplexed
address inputs permit both a reduction in pins to the stand-
ard l6-pin package configuration and an increase in system
densities. In addition to the RAS only refresh mode, the
Hidden refresh mode and CAS before RAS refresh mode
are available.
FEATURES
Type name
Access time
(max)
(ns)
Cycle time
(min)
(ns)
Power dissipation
(typ)
(mW)
M5M4257S-12
120
230
260
M5M4257S-15
150
260
230
M5M4257S-20
200
330
190
• Standard l6-pm package
• Single 5V±10% supply
• Low standby power dissipation: 22mW (max)
• Low operating power dissipation:
M5M4257S-12 ........... 413mW (max)
M5M4257S-15 ........... 385mW (max)
M5M4257S-20 ........... 303mW (max)
• Unlatched output enables two-dimensional chip selec-
tion
PIN CONFIGURATION (TOP VIEW)
ADDRESS INPUT As'" I
DATA INPUT
WRITE
CONTROL INPUT
ROW ADDRESS RAS -+ 4
STRO::~::~:1:: ::
INPUTS
A1 .... 7
(5V) Vee
Vss (OV)
15 ... CAS mg~~ I~~B~ESS
DATA OUTPUT
Outline 16S1
• Early-write operation gives common I/O capability
• Read-modify-write, RAS-only-refresh, Nibble-mode
capabilities. (Pin 1 is used for nibble mode)
• CAS before RAS refresh mode capability
• All input terminals have low input capacitance and are
directly TTL-compatible
• Output is three-state and directly TTL-compatible
• 256 refresh cycles every 4ms. Pin 1 is not needed for
refresh.
• CAS controlled output allows hidden refresh
APPLICATION
• Main memory unit for computers
• Microcomputer memory
BLOCK DIAGRAM
DATA INPUT
WR ITE CONTROL
INPUT
0 2 r--------------------------,
w 3r--------------~
I
~Vee(5V)
ADDRESS
INPUTS
I
1V~(",J
cr;
a:
32K w
32K
a:
32K w
32K
oill
8A2
MEMORY
ARRAY
0
u0
w
MEMORY
ARRAY
MEMORY
ARRAY
0
u0
w
MEMORY
ARRAY
oill
0
0
ill
-!
A3 ~S=====~~=====F====~_+=====t_Jz''""
A4
As
~t=====~COiLUrM=N ====F====~DE_COtDE,R====~_,~>'u5-
'" '" 8A6
~------,_g JA7
32K 32K 32K 32K
MEMORY
ARRAY
0
a:
MEMORY MEMORY
ARRAY
ARRAY
a0:
MEMORY
ARRAY
o-!
cr;
z>-
I
• MITSUBISHI
.... ELECTRIC
2-125
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Pages | Pages 15 | ||
Télécharger | [ M5M4257S-15 ] |
No | Description détaillée | Fabricant |
M5M4257S-12 | 256K-Bit DRAM | Mitsubishi |
M5M4257S-15 | 256K-Bit DRAM | Mitsubishi |
US18650VTC5A | Lithium-Ion Battery | Sony |
TSPC106 | PCI Bus Bridge Memory Controller | ATMEL |
TP9380 | NPN SILICON RF POWER TRANSISTOR | Advanced Semiconductor |
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