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M5M42S6S-15 fiches techniques PDF

Mitsubishi - 256K-Bit DRAM

Numéro de référence M5M42S6S-15
Description 256K-Bit DRAM
Fabricant Mitsubishi 
Logo Mitsubishi 





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M5M42S6S-15 fiche technique
MITSUBISHI LSls
MSM42S6S-12, -15, -20
262 144-BIT (262 144-WORD BY 1-BIT) DYNAMIC RAM
DESCRIPTION
This is a family of 262 144-word by 1-bit dynamic RAMs,
fabricated with the high performance N-channel silicon gate
MOS process, and is ideal for large-capacity memory
systems where high speed, lOiN power dissipation, and low
costs are essential. The use of double-layer polysilicon
process combined with silicide technology and a single-
transistor dynamic storage cell provide high circuit density
at reduced costs, and the use of dynamic circuitry including
sense amplifiers assures low power dissipation. Multiplexed
address inputs permit both a reduction in pins to the stand-
ard 16-pin package configuration and an increase in system
densities. In addition to the RAS only refresh mode, the
Hidden refresh mode and CAS before RAS refresh mode
are available.
FEATURES
Type name
Access time
(max)
(ns)
Cycle time
(min)
(ns)
Power dissipation
(typ)
(mW)
M5M4256S-12
120
230
260
M5M4256S-15
150
260
230
M5M4256S-20
200
330
190
• Standard 16-pin package
• Single 5V±10% supply
• Low standby power dissipation: 22mW (max)
• Low operating power dissipation:
M5M4256S-12··········· 413mW (max)
M5M4256S·15 ........... 385mW (max)
M5M4256S-20 ........... 303mW (max)
• Unlatched output enables two-dimensional chip selec-
tion and extended page boundary.
PIN CONFIGURATION (TOP VIEW)
ADDRESS INPUT As'" 1
DATA INPUT
WRITE
CONTROL INPUT
ROW ADDRESS RAS .... 4
STROBE INPUT
ADDRESS
INPUTS
A,
(5V) Vee
Vss (OV)
15 +-- CAS ~~~g~~ I~~~~ESS
s: DATA OUTPUT
.'s.".:.
N
'"en
(J)
ADDRESS
INPUTS
Outline 16S1
• Early-write operation gives common I/O capability
• Read-modify-write, RAS-only-refresh, Page-mode capa-
bilities
• CAS before RAS refresh mode capability
• All input terminals have low input capacitance and are
directly TTL-compatible
• Output is three-state and directly TTL-compatible
• 256 refresh cycles every 4ms. Pin 1 is not needed for
refresh.
• CAS controlled output allows hidden refresh
APPLICATION
• Main memory unit for computers
• Microcomputer memory
BLOCK DIAGRAM
DATA INPUT
WRITE CONTROL
INPUT
ADDRESS
INPUTS
---------
0 2 }--------------------------,
W3)-------------=~l_----~-1
INPUT
LATCH
I
1- ¢ v eCC 5V)
I
v",''''
32K
0:
w
32K
32K
0:
w
32K
Az
MEMORY
ARRAY
0
0
u
w
0
MEMORY
ARRAY
MEMORY
ARRAY
0
0
u
w
0
MEMORY
ARRAY
f::
::0
u
A3
0:
U
.J
A4
COLUMN
DECODER
0
0:
Q DATA
As
fz- OUTPUT
u0
As
32K
MEMORY
S
0
32K 32K
MEMORY MEMORY
S
0
32K
MEMORY
§'
ARRAY
0:
ARRAY
ARRAY
0:
ARRAY
_ JI
L...--L------
2-110
.• MITSUBISHI
.... ELECTRIC

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