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PDF M5M5117P-15 Data sheet ( Hoja de datos )
| Número de pieza | M5M5117P-15 | |
| Descripción | 16K-Bit CMOS Static RAM | |
| Fabricantes | Mitsubishi | |
| Logotipo |  |
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MITSUBISHI LSls
M5M5117P, -15
16384-BIT (2048-WORD BY 8-BIT) CMOS STATIC RAM
DESCRIPTION
The M5M5117P series of 2048-word by a-bit asynchronous
silicon gate CMOS static RAM operates on a single 5V
power supply and is designed for easy use in applications
requiring battery backup_
A chip select input, S, is available to provide the mini-
mum standby current with battery back-up while an output
enable input, OE, enables high-speed memory access_
The series features pin compatibility with the M5L2716K
16K EPROM and M58725P 16K static RAM, and it is
packaged in a standard 24-pin plastic DIL package_
FEATURES
Type name
Access time
(max)
M5M5117P-15
M5M5117P
lS0ns
200ns
-
OE access
time
(max)
80ns
lOOns
Current consumption
Active
(max)
Stand-by
(max)
SOmA
lS/lA
• Single 5V power supply_
• External clock and refresh operation not required_
• Data can be held with 2V supply voltage_
• All inputs, and outputs are directly TTL compatible_
• All outputs are 3-state with OR-tie capability_
• Easy expansion of memory capacity with chip select
signal.
• Common input/output for data pins.
• Pin compatibility with M5L2716K 16K EPROM and
M58725P 16K static RAM.
APPLICATIONS
Battery drive, small-capacity memory units with battery
back-up
PIN CONFIGURATION (TOP VIEW)
A7 - \
ADDRESS
INPUTS
A.
A,
A,
Al
Ao
IDATA DOl
INPUTS/I DO,
OUTPUTS DO,
(DV) GND
Vcc(5V)
23 ~ As I ADDRESS
I" ~ A, INPUTS
w21 ~
~~ITi CONTROL
20 ~ 6E ?NUp1]'+JT ENABLE
" ~ AID ADDRESS INPUT
CHIP SELECT
INPUT
DATA
INPUTS/
OUTPUTS
Outline 24P4
FUNCTION
The M5M5117P series has a 2048-word by 8-bit configura-
tion. It operates on a single 5V supply and its inputs/
outputs are directly TTL compatible. Its completely static
circuitry obviates the need for external clock and refresh
operations and makes it very easy to use.
The data of the DO pin are written when the address is
designated by address signals Ao - AIO , the S signals turns
low-level, and the W signal is set low.
When for the reading operation the W signal is set high,
the Sand OE signals are set low, pin DO is set to the output
mode and the address is designated by signals Ao - AIO ,
the data of the designated address are output to pin DQ.
BLOCK DIAGRAM
ADDRESS INPUTS
,.--
-
r--
- r--
1
A, 1)------>
A, 2~~
c:
UJ
*~ ~As
3)------>
c:
D
A. 4)------> Dc:
D
0
U
UJ
s:A, 5
A, ~2
A, ~3
«UJ
:;dt
0:::>
c:1D
D
a0:
+--_+T----,_-t----+-T-'~---f--.Tf____'o1-++++1-++,..--.-.(1"-T
2048-WORD
X 8-BIT RAM
(128 ROWS X 128
COLUMNS)
~ ~ h----->(,~ ~~;
~ f-+h-----o(jll 003
:-. ~ ~ ID
13 DO.
« I • - f-
14 005
UJ 12
15 DO,
~~
16 007
DO,
.~~ ~A2 6
Al 7
o~ a:
«~ 8 ~ ~
Ao 8
-+=-Zill
:2(J)
=>0
...JU
:J(I)
Ow
A 10 19
6~ uo
16
I
I
, ~-
DATA
INPUTS/OUTPUTS
WRITE CONTROL INPUT Vi r21)--Tr =FV::f}---+--------..J
~ ---------......JTCHIP SELECT INPUT S
.-o[)>----......
~VCC(5V)
12 GND (DV)
OUTPUT ENABLE INPUT OE ~ ~}------~----------'
'-------- --- - --- - --- - --- - ------'
• MITSUBISHI
~ELECTRIC
4-13
1 page  
MITSUBISHI LSls
M5M5117P, -15
16384-BIT (2048-WORD BY 8-BIT) CMOS STATIC RAM
Write cycle (S control)
tew
Ao-A 10
tsu IA)
tsu ISj
tw (W)
DO,-DOg
(DATA IN)
DO,-DOg
(DATA OUT)
OE = LOW LEVEL
Note 4' Test conditions
Input pulse level 0.4 "'-' 2.4V
Input pulse risetime and falltime 10ns
Load: nT L. CL ~ 100pF
Reference level: 1.5V
DATA
Note 5: Hatching indicates the don't care inputs.
6: Writing is performed while Sand Ware in the low-level
overlap period.
7: The output is kept in the high-impedan~e state when W
fa Us simultaneously with, or before, the S falls.
8: A reverse phase signal should not be supplied when 00
is in the output mode.
POWER-DOWN CHARACTERISTICS
Vee
VCCIPDI
• MITSUBISHI
...... ELECTRIC
4-17
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| Páginas | Total 5 Páginas | |
| PDF Descargar | [ Datasheet M5M5117P-15.PDF ] | |
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