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M5M5165P-12 fiches techniques PDF

Mitsubishi - 64K-Bit CMOS Static RAM

Numéro de référence M5M5165P-12
Description 64K-Bit CMOS Static RAM
Fabricant Mitsubishi 
Logo Mitsubishi 





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M5M5165P-12 fiche technique
~SMs16sP-70,
-10,
MITSUBISHI LSls
-12, -15,
-70L, -10L, -12L, -lsL
6SS36-BIT (8192 WORD BY 8-BIT) CMOS STATIC RAM
DESCRIPTION
The M5M5165P is a 65,536-bit CMOS static RAM orga-
nized as 8,192 words by 8 bits which is fabricated using
high-performance double polysilicon CMOS technology.
The use of resistive load NMOS cells and CMOS periferals
result in a high-density and low-power static RAM. It is
ideal for the memory systems which require simple interface.
The stand-by current is low enough for a battery back-
up application. It is mounted in a standard 28 pin package
and configured in an industrial standard 8K x 8-bit pinout.
FEATURES
Type
Access time
(max)
Power supply current
Active
(max)
Stand-by
(max)
M5M5165P-70
M5M5165P-l0
M5M5165P-12
M5M5165P-15
M5M5165P-70L
M5M5165P-l0L
M5M5165P-12L
M5M5165P-15L
70ns
lOOns
120ns
150ns
70ns
lOOns
120ns
150ns
50mA
2mA
100,uA
• Single +5V Power Supply
• Fully Static Operation: No Clocks, No Refresh
• Data-Hold on +2V Power Supply
• Directly TTL Compatible: All Inputs and Outputs
• Three-State Outputs: OR-tie Capability
• Simple Memory Expantion by s;- , S2
• OE Prevents Data Contention in The I/O Bus
• Common Data I/O
• Pinout Compatible with 64K EPROM M5L2764K
APPLICATION
Small Capacity Memory Units.
FUNCTION
The operation mode of the M6M5165P is determined by a
Specification of 70. 70L are subject to change.
PIN CONFIGURATION (TOP VIEW)
NO
ADDRESS
INPUT
Vee (5V)
W t~~~~OL INPUT
S2 CHIP SELECT
A }INPUT
A9s
ADDRESS
INPUT
All
at ~~l~~~ INPUT
A10 ADDRESS INPUT
:~:: ~~j:~::m
6 .... D05
5 .... D04
L-_ _ _- - '
NC : NO CONNECTION
Outline 28P4
combination of the device control inputs S" S2, Wand OE.
Each mode is summarized in the function table. (see next page)
A write cycle is excuted whenever the low level W
overlaps with the low level S, and the high level S2. The
address must be set up before the write cycle and must be
stable during the entire cycle. The data is latched into a cell
on the trailing edge of W, 5, or S2, whichever occurs first,
requring the set-up and hold time relative to these edge to
be maintained. The Output enable input OE directly
controls the output stage. Setting the OE at a high level,
the output stage is in a high-impedance state, and the data
bus contention problem in the write cycle is eliminated.
A read cycle is excuted by setting W at a high level and
OE at a low level while Sf and S2 are in an active state (S; = L,
BLOCK DIAGRAM
A9
A8
A'2
A7
A6
A5
A4
A3
ADDRESS INPUT
8192 WORDS x
8 BITS
(256 ROWS x
256 CO LUMNS)
DATA 1/0
A2
AI 32
Ao
WRITE CONTROL
INPUT
All
W
OUTPUT ENABLE
INPUT
-.:~Jvec (5V)
GND (OV)
..
.
.
.
MITSUBISHI
ELECTRIC
4-33

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