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PDF M5M4256P-15 Data sheet ( Hoja de datos )
| Número de pieza | M5M4256P-15 | |
| Descripción | 256K-Bit DRAM | |
| Fabricantes | Mitsubishi | |
| Logotipo |  |
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MITSUBISHI LSls
M5M4256P-12, -15, -20
262 144-BIT (262 144-WORD BY I-BIT) DYNAMIC RAM
DESCRIPTION
This is a fami Iy of 262 144-word by 1-bit dynamic RAMs,
fabricated with the high performance N-channel silicon gate
MOS process, and is ideal for large-capacity memory
systems where high speed, low power dissipation, and low
costs are essential. The use of double-layer polysilicon
process combined with silicide technology and a single-
transistor dynamic storage cell provide high circuit density
at reduced costs, and the use of dynamic circuitry including
sense amplifiers assures low power dissipation_ Multiplexed
address inputs permit both a reduction in pins to the stand-
ard 16-pin package configuration and an increase in system
densities. In addition to the RAS only refresh mode, the
Hidden refresh mode and CAS before RAS refresh mode
are available.
FEATURES
Type name
Access time
(max)
(ns)
Cycle time
(min)
(ns)
Power diSSipation
(typ)
(mW)
M5M4256P-12
120
230
260
M5M4256P-15
150
260
230
M5M4256P-20
200
330
190
• Standard 16-pln package
• Single 5V±10% supply
• Low standby power dissipation: 25mW (max)
• Low operating power dissipation:
M5M4256P-12 ........... 360mW (max)
M5M4256P-15 ........... 330mW (max)
M5M4256P-20 ........... 275mW (max)
• Unlatched output enables two-dimensional chip selec-
tion .and extended page boundary.
PIN CONFIGURATION (TOP VIEW)
ADDRESS INPUT As" 1
DATA INPUT
WRITE
CONTROL INPUT
ROW ADDRESS RAS .. 4
STRO::~::~:1:: ::
INPUTS
A, .. 7
(5V) Vee
Vss (OV)
15 +- CAS ~~~g~~ 1~~3~ESS
DATA OUTPUT
Outline 16P4
• Early-write operation gives common I/O capability
• Read-modify-write, RAS-only-refresh, Page-mode capa-
bilities
• CAS before RAS refresh mode capability
• All input terminals have low input capacitance and are
directly TTL-compatible
• Output is three-state and directly TTL-compatible
• 256 refresh cycles every 4ms. Pin 1 is not needed for
refresh.
• CAS controlled output allows hidden refresh
APPLICATION
• Main memory unit for computers
• Microcomputer memory
BLOCK DIAGRAM
DATA INPUT D 2 } - - - - - - - - - - - - - - - - - - - - - - - - - - - ,
WRITE CONTROL
INPUT
W 3 r------~-------___<I
COL~~R~~~~~~0~ CAS
INPUT
LATCH
I
~VCcC5V)
ROW ADDRESS
STROBE INPUT
ADDRESS
INPUTS
I
a:
32K w
32K
a:
32K w
32K
1'"' ''=A2
MEMORY
ARRAY
0
0uw
MEMORY
ARRAY
MEMORY
ARRAY
0
u0w
MEMORY
ARRAY
0 0 u::J
A3
a:
U
.J
A4
COLUMN
DECODER
a0:
As
Iz-
u0
A6
'S32K 32K 32K 32K
MEMORY
" "ARRAY
0a:
MEMORY
ARRAY
MEMORY
ARRAY
0a:
MEMORY
ARRAY
I
~,------_J
2-80
• .MITSUBISHI
. . . . ELECTRIC
1 page  
MITSUBISHI LSls
M5M4256P-12, -15, -20
262144~BIT (262 144·WORD BY I.BIT) DYNAMIC RAM
TIMING REQUIREMENTS (For Read, Write, Read-Modify-Write, Refresh, and Page-Mode Cycle)
=(Ta = 0 - 70°C, Vee 5V 1:: 10%. VSS =OV. unless otherwise noted, See notes 5, 6 and 7)
Symbol
Parameter
IORF
I W(RASH)
IW(RASL)
I W(CASL)
I W(CASH)
Ih (RAS-CAS)
Ih (CAS-RAS)
td (CAS-RAS)
Id (RAS-CAS)
Isu (RA-RAS)
Isu (CA-CAS)
I h (RAS-RA)
I h (CAS-CA)
I h (RAS-CA)
I THL
I TLH
Refresh cycle time
RAS high pulse width
RAS low pulse width
CAS low pulse width
CAS high pulse width
CAS hold time after RAS
RAS hold time after CAS
Delay time, CAS to RA'S
Delay time, RAS to CAS
Row address setup time before RAS
Column address setup time before CAS
Row address hold time a1ter RA'S
Column address hold time after CAS
Column address hold time after RAS
'Transiti'on time
(Note 8)
(Note 91
(Note 101
Alternative
Symbol
IREF
I RP
I RAS
I CAS
ICPN
ICSH
I RSH
I CRP
I RCD
I ASA
IASC
IRAH
ICAH
IAR
IT
Limits
M5M4256P-12 M5M4256P-15 M5M4256P-20
Min Max Min Max Min Max
44
4
100 100 120
120 10000 150 10000 200 10000
60 75 100
30 35 40
120 150 200
60 75 100
30 30 40
20,
60 25
75 30
100
0 0a
~5
~5
~5
15 ,20 25
20 25 35
80 100 135
3 50 3 50 3 50
Note 5
6
9
10
An initial pause of 500J,ls is required after power,uJj followed by any eight RAS or RAS/CAS cycles before proper device operation is achieved.
The switching characteristics are defined as t THL = t TLH = 5ns.
Reference levels of input signals are VIH min. and VIL max. Reference levels for transition time are also between VIH and VIL.
Except for page-mode.
td (CAS-RAS) reqUirement is applicable for all RAS/CAS cycles.
Operation within the t d (AAS-CAS) max limit insures that ta (RAS) max can be met. 1d (AAS-CAS)maX is specified reference point only;if
td (RAS-CAS) is greater than the specified td (AAS-CAS) max limit, then access time is controlled exclusively by ta (CAS).
+ +td (AAS-CAs)mln = 1h (AAS-AA)mm 21 THL(t TLH) 1 5U(CA-CAS)mm_
Unit
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SWITCHING CHARACTERISTICS (Ta=0-70·C. Vcc=5V±10%, VSs=OV, unlessotherw,senoted)
Read Cycle
Symbol
lOR
I su (R-CAS)
Ih (CAS-R)
Ih( RAS-R)
Id,s (CAS)
ta (CAS)
la(RAS)
Parameter
Read cycle time
Read setup time before CAS
Read hold time after CAS
Read hold time after R7i:S
Output disable time
CAS access time
RAS access time
(Note 11)
(Note 111
(Notel21
(Note 13)
(Note t4)
Alternative
Symbol
I RC
I RCS
I RCH"
IARH
IOFF
ICAC
IRAC
Limits
M5M4256P -12 M5M4256P-15 M5M4256P-20
Min
Max
Min
Max
Min
Max
230 260 330
0 00
0 00
20 20 25
0 35
0 40
0 50
60 75 100
120 150 200
Unit
ns
ns
ns
ns
ns
ns
ns
Note 11
12
13
14
Either t h (AAS- A) or t h (CAS-A) must be satisfied for a read cycle.
tdls (CAS)maX defines the time at which the output achieves the open circuit c.ondition and is not reference to VOH or VOL
This is the value when 1d (AAS-CAS)~td (AAS-CAS)max. Test conditions; Load = 2TTL, CL = 100pF
This is the value when t d (RAS-c"AS)< t d (RAS-CAS)max. When t d (AAS-CAS)~ t d (RAS-CAS)maX, ta (RAS) will increase by the amount that
t d (AAS-CAS) .exceeds the value shown Test conditions; Load = 2T TL, CL = 100pF
Write Cycle
Symbol
Parameter
loW
ts u (W-CAS)
Ih(CAS-W)
Ih (RAS-W)
Ih (W-RAS)
Ih(W-CAS)
Iw(w)
I su (D-CAS)
Ih (CAS-D)
Ih(RAS-D)
Write cycle time
Write setup time before CAS
Write hold time after CAS
Write hold time after RAS
RAS hold time after write
CAS hold time after write
Write pulse width
Data·in setup time before CAS
Data-in hold time after CAS
Data-in hold time after RAS
'(Note 17)
Alternative
Symbol
t RC
I WCS
IWCH
IWCR
I RWL
ICWL
IWp
IDS
IDH
IDHR
Limits
M5M4256P-12 M5M4256P-15 M5M4256P-20
Min Max Min Max Min Max
230 260 330
~10
~10
~10
40 45 55
100 120 155
40 45 55
40 45 55
40 45 55
a a0
30 35 40
90 110 140
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2-84
• MITSUBISHI
"ELECTRIC
5 Page 
MITSUBISHI LSls
M5M4256P-12, -IS, -20
262 144-BIT (262 144-WORD BY I-BIT) DYNAMIC RAM
TYPICAL CHARACTERISTICS
NORMALIZED ACCESS TIME
VS.SUPPLY VOLTAGE
1.3
U..;
~ 1.2
.:J
LW
2
i=
1.1
<f>
<f>
..LW
uU 1.0
0
..LW
N
0.9
~
2
0:
0z
O.S
Ta ~25'C
I\.
\
~
I~
f'...
....... t--
0.7
4.0 5.0 6.0
SUPPLY VOLTAGE Vee (V)
NORMALIZED ACCESS TIME
VS. AMBIENT TEMPERATURE
1.3
.Vi
!5 1.2
.:J
LW
Vee~5.oVI
./
V
2
i=
1.1
V
<f>
<f>
..LW
U
u
1.0
0
/
V
.. '"t.W
N
0.9
~
2
0: O.S
0z
0.7_ 20 0
20 40 60 SO 100
AMBIENT TEMPERATURE Ta ('C)
ACCESS TIME VS. LOAD
CAPACITANCE
25
II
Vee=4.5V
_ Ta=25'C
Vl 20
S
.U;
c: 15
.:J
<l
LW ;
'2
i=
10
<f>
.. /<f>
LW
U
U
0
..-
/
/ V '"
-5
100 200 300 400 500 600
LOAD CAPACITANCE ,CL (pF)
OPERATING CURRENT
VS. SUPPLY VOLTAGE
SO
« Ta l=25,cl
-S 70 f--1eR=260ns
"-Q 60
rz-
LW
0: 50
0:
::J
U
..';-;;': 40
r-
0:
/tno.W- 30
VV
/
./
/'"
20
4.0
5.0
6.0
SUPPLY VOLTAGE Vee (V)
OPERATING CURRENT
VS, AMBIENT TEMPERATURE
"Q SO~--+---+---+---+---+-~
rz-
LW
0:
40~--+---+---+---+---+-~
0:
::J
U
'-' 30~--+---+---+---+---+-~
Z
~
0:
oLnW-
20~--+---+---+---+---+-~
10 _L.....,.,ZO,...-LO--""'Zl.,.0--4l.,.0-""'6'!"0-""'Sl.,.0--}100
AMBIENT TEMPERATURE Ta (,C)
OPERATING CURRENT
VS. CYCLE RATE
60 I
Vec=5.5V
50 f-- Ta=2S'C
"Q
40
rz-
LW
0:
30
0:
::J
U
'-' 20
Z
~
0:
iof
10
/
V
/
V
/
V
/
"
o
23
/
CYCLE RATE 1/1 eR (MHz)
6
2-90
• MITSUBISHI
"ELECTRIC
11 Page | ||
| Páginas | Total 15 Páginas | |
| PDF Descargar | [ Datasheet M5M4256P-15.PDF ] | |
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