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PDF M5M4416P-15 Data sheet ( Hoja de datos )
| Número de pieza | M5M4416P-15 | |
| Descripción | 64K-Bit Dynamic Ram | |
| Fabricantes | Mitsubishi | |
| Logotipo |  |
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MITSUBISHI LSls
MSM4416P-12, -15
65 536-BIT (16 384-WORD BY 4-BIT) DYNAMIC RAM
DESCRIPTION
This is family of 16348-word by 4-bit dynamic RAMs,
fabricated with the high performance N-channel silicon-gate
MOS process, and is ideal for large-capacity memory
systems where high speed, low power dissipation, and low
costs are essential. The use of double-layer polysilicon
process technology and a single-transistor dynamic storage
cell provide high circuit density at reduced costs, and the
use of dynamic circuitry including sense amplifiers assures
low power dissipation. Multiplexed address inputs permit
both a reduction in pins to the standard 18-pin package
configuration and an increase in system densities. The
M5M4416P operates on a 5V power supply using the
on-chip substrate bias generator.
FEATURES
• Performance ranges
Type name
M5M4416P-12
M5M4416P-15
Access time
(max}
(ns)
120
150
Cycle time
(min)
Insl
220
260
Power dissipation
Itypi
ImWI
175
150
• 16,384 x 4 Organization
• Industry standard 18-pin dual in line package
• Single 5V ±10% supply
• Low standby power dissipation:
25mW (max)
• Low operating power dissipation:
M5M4416P-12 275mW (max)
M5M4416P-15 250mW (max)
PIN CONFIGURATION (TOP VIEW)
OUTPUT ENABLE 0 E --> 1
INPUT
DATA IN/{DQ1." 2
DATA OUT DQz'" 3
WRITE -
CONTROL INPUT W --> 4
ROW ADDRESS RAS --> 5
STRO:~~;;;~T { ::: :
(5V)
A4 --> 8
Vee
Vss (Ov)
17 H DQ4 g~iA IN/DATA
16 ..... CAS COLUMN ADDRESS
STROBE INPUT
DATA IN/DATA
OUT
ADDRESS INPUTS
lAo & A,-··ROW
ADDRESS
Only I
Outline 18 P4
• All Inputs, outputs TTL compatible and low capacitance
• 3-State unlatched outputs
• 128 refresh cycles/2ms. Pin 10 is not needed for refresh
• Early write or OE to control output buffer impedance
• Read-Modify-Write, RAS-only refresh, Hidden refresh
and Page mode capabilities
• Wide RAS pulse width for Page mode ..... 30j.ts max
APPLICATION
• Refresh memory for CRT
BLOCK DIAGRAM
COLSUTMRNOBAEDDINRPESUST CAS 16}. ----------~r;:;_;;_;7;;;,:;;;;;;:;:;;-,
ROW ADDRESS RAS 5 }-----------IL...,....::.:.:,:::.:..:__.J
STROBE INPUT
'
WRITE Vi 4 ) - - - - - - - - - - - - + - - - - - - < t - . J
CONTROL INPUT
COLUMN DECODER
ADDRESS INPUTS
a:
ouow
ow
~
a:
L - - _____
SENSE REFRESH
AMPLIFIER & I/O CONTROL
MEMORY CELL
165.536 BITSI
• MITSUBISHI
~ELECTRIC
.~Vee(5V)
r~("')
DDQQz 1} DATA
INPUTS/
DQ3 OUTPUTS
DQ4
OUTPUT ENABLE
INPUT
2-65
1 page  
MITSUBISHI LSls
M5M4416P-12, -15
65 536-BIT (16 384-WORD BY 4.BIT) DYNAMIC RAM
SWITCHING CHARACTERISTICS (Ta=0-70'C, Voo=5V±10%, VSs=OV, unless otherwise noted)INote 5)
Symbol
Parameter
Alternative
Symbol
M5M4416P-12
Limits
Min Max
M5M4416P-15
Limits
Min Max
Unit
ta(o)
la (R)
la(OE)
IdiS(OH)
Idls(OE)
Access ti me from CAS
Access time from RAS
Access time from OE
Output disable time after CAS high
Output disable time after OE high
INote 6,7)
INote 6,8)
INote 6)
INote 9)
INote 9)
10AO
I RAO
-
IOFF
-
60 75 ns
120 150 ns
30 40 ns
0 25 0 30 ns
0 25 0 30 ns
Note 5: An initial pause of 500~s is required after power-up followed by any 8 RAS or RAS/CAS cycles before proper device operation is achieved.
Note that RAS may be cycled during the initial pause.
And any 8 RAS or RAS/CAS cycles are required after prolonged periods (greater than 2ms) of RAS inactivity before proper device operation is achieved.
6: Measured with a load circuit equivalent to 2TTL loads and 100pF.
7: Assume that tRCCL ~ tRLCL max.
<8: Assume that tRLCL tRLCL max. If tRLCL is greater than tRLCL max then ta(R) will increase by the amount that tRLCL exceeds tRLCL max.
9: tdis(CH) max and tdis(OE) max define the time at which the output achieves the high impedance state (IOUT~ \±10J.1Aj) and are not reference to VOH
min or VOL max.
TIMING REQUIREMENTS (For Read, Write, Read-Modify-Write, Refresh, and Page-Mode Cycles)
(Ta=0-70'C, Voo=5V±10%, VSs=OV, unless otherwise noted, See notes 10,11)
Symbol
Parameter
Alternative
Symbol
M5M4416P-12
Limits
Min Max
M5M4416P-15
Limits
Min Max
Unit
10(RF)
Refresh cycle time
I REF
2 2 ms
IW(RH)
RAS high pulse width
I RP 90 100 ns
I RLOL
Delay time, RAS low to CAS low
INote 12) I ROD
25 60
30 75
ns
10HRL
Delay time, CAS high to RAS low
INote 13) 10RP
-20
-20
ns
Isu (RA)
Isu (OA)
Row address setup time before RAS low
Column address setup time before CAS low
IASR
IASO
0
0
0 ns
0 ns
Ih(RA)
Row address hold time after RAS low
I RAH
15
20 ns
Ih(OLOA) Column address hold time after CAS low
10AH
20
25 ns
Ih(RLOA) Column address hold time after RAS low
IAR
80
100
ns
IT Transition time (rise and fa\l)
INote 14) IT
3 50
3 50
ns
Note 10:
11:
12:
13:
14:
The timing requirements are assumed tT=5ns.
VIH min and VIL max are reference levels for measuring timing of input signals.
tRLCL max is specified as a reference point only; if tRLCL is less than tRLCL max, access time is ta(R), if tRLCL is greater than tRLCL max, access time is
tRLCL + taco)· tALCL min is specified as tRLCL min. = th(RA) + 2 tT + tSU(CA).
tCHRL requirement is only applicable for RAS/CAS cycles preceeded by a CAS only cycle (i.e., For systems where CAS has not been decoded with RAS).
tT is measured between V'H min and V'L max.
Read and Refresh Cycles
Symbol
Parameter
Alternative
Symbol
10 (rd)
IW(RL)
IW(OL)
tW(OH)
Ih (RLOH)
Ih (CLRH)
Isu (rd)
Ih(OHrd)
Ih(RHrd)
Ih(OEOH)
Ih (OERH)
th (OLOE)
Ih (RLOE)
tOOEL
IOEHD
IRHO L
Read cycle time
RAS low pulse width
CAS low pulse width
CAS high pulse width
CAS hold time after RAS low
RAS hold time after CAS low
Read setup time before CAS low
Read hold time after CAS high
Read hold time after RAS high
CAS hold time after DE low
RAS hold time after OE low
OE hold time after CAS low
OE hold time after RAS low
Delay time, Data to DE low
Delay time~ OE high to Data
Delay time, RAS high to CAS low
INote 15)
INote 15)
IRO
IRAS
10AS
10PN
10SH
I RSH
IROS
I ROH
I RRH
-
-
-
-
-
-
-
Note 15: Either th(CHrd) or th(RHrd) must be satisfied for a read cycle.
M5M4416P-12
Limits
Min Max
220
120 10000
60
30
120
60
0
0
10
30
30
60
120
0
25
0
M5M4416P-15
Limits
Min Max
260
150 10000
75
30
150
75
0
0
10
40
40
75
150
0
30
0
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
• MITSUBISHI
.... ELECTRIC
2-69
5 Page 
MITSUBISHI LSI.
M5M4416P.12, ·,15
6S S36·BIT (16 384·WORD BY 4·BIT) DYNAMIC RAM
Read-Write and Read-Modify-Write Cycles
to(rdW)
th(RLCH)
tW(RL)
VIH
VI L _.JV,"'V"',,_ _-.II
w
DQ1- D Q4
(INPUTS)
DQ1- D Q4
(OUTPUTS)
th(RLOE)
• MITSUBISHI
. . . . ELECTRIC
2-75
11 Page | ||
| Páginas | Total 15 Páginas | |
| PDF Descargar | [ Datasheet M5M4416P-15.PDF ] | |
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