M5K4164ANP-15 Datasheet PDF - Mitsubishi
| Part Number | M5K4164ANP-15 | |
| Description | 64K-Bit DRAM | |
| Manufacturers | Mitsubishi | |
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MITSUBISHI LSls
M5K4164ANP-12, -15
65 536-BIT (65 536-WORD BY I-BIT) DYNAMIC RAM
DESCRIPTION
This is a family of 65 536-word by l-bit dynamic RAMs,
fabricated with the high performance N-channel silicongate
MOS process, and is ideal for large-capacity memory
systems where high speed, low power dissipation, and low
costs are essential. The use of double-layer polysilicon
process technology and a single-transistor dynamic storage
cell privide high circuit density at reduced costs, and the
use of dynamic circuitry including sense amplifiers assures
low power dissipation. Multiplexed address inputs permit
both a reduction in pins to the standard 16-pin package
configuration and an increase in system densities. The
M5K4164ANP operates on a 5V power supply using the
on-chip substrate bias generator.
FEATURES
• High speed
Type name
M5K4164ANP-12
M5K4164ANP-15
Access time
(max)
(ns)
120
150
Cycle time
(min)
(ns)
220
260
Power dissipation
(typ)
(mW)
175
150
• Single 5V±100/0-supply
• Low standby power dissipation:
22mW (max)
• Low operating power dissipation: 300mW (max)
• Unlatched output enables two-dimensional chip selec-
tion and extended page boundary
• Early-write operation gives common I/O capability
• Read-modify-write, RAS-only refresh, and page-mode
capabilities
• All input terminals have low input capaciatance and are
directly TTL-compatible
PIN CONFIGURATION (TOP VIEW)
DATA INPUT
WRITE
CONTROL INPUT
ROW ADDRESS
STROBE INPUT
NC
ADDRESS INPUTS
(5V)
Vss (OV)
15 +- CAS ~~~g~EN 1~~8fESS;
14 -+Q DATA OUTPUT
ADDRESS INPUTS
Outline 16P4
• Output is three-state and directly TTL-compatible
• 128 refresh cycles every 2ms
(16K dynamic RAMs M5K4116P, S compatible)
• CAS controlled output allows hidden refresh
• Output data can be held infinitely by CAS
• Interchangeable with Mostek's MK4564 and
Motorola'S MCM6665 in pin configuration
APPLICATION
• Main memory unit for computers
BLOCK DIAGRAM
DATA INPUT
WRITE CONTROL INPUT
COLL~~R~:f?~~3f CAS
ROW ADDRESS
STROBE INPUT
AO
ADDRESS INPUTS
COLUMN DECODER
MEMORY CELL
(64 ROWS X 256 COLLUMNS
SENSE REFRESH AMPLIFIER
MEMORY CELL
(64 ROWS X 256 COLUMNS)
COLUMN DECODER
MEMORY CELL
164 ROWS X 256 COLUMNS)
SENSE REFRESH AMPLIFIER
(64 ROMWESMXOR2Y56CCEOLLUMNS)
COLUMN DECODER
Vee (5V)
Vss (OV)
J'
2-14
• MITSUBISHI
...... ELECTRIC
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MITSUBISHI LSls
M5K4164ANP·12, ·15
65 536-BIT (65 536-WORD BY I-BIT) DYNAMIC RAM
TIMING REQUIREMENTS (For Read, Write, Read-Modify-Write, Refresh, and Page-Mode Cycle)
=(Ta = 0 -70GC. Vee sv ± 10%, Vss = OV. unless otherwise noted. See notes 5, 6 and 7)
Symbol
Parameter
Alternative
Symbol
M5K4164ANP-12
Limits
Min Max
M5K4164ANP-15
Limits
Min Max
Unit
leRF
I W(RASH)
I W(RASU
t W(CASU
t W(CASH)
I h (RAS-CAS)
I h (CAS- RAS)
Id (CAS-RAS)
I d (RAS-CAS)
I SU(RA-RAS)
Refresh cycle time
RAS high pulse width
RAS low pulse width
CAS low pulse width
CAS high pulse width
(NoteSI
CAS hold time after RAS
RAS hold time after CAS
Delay time, CAS to RAS
Delay time, RAS to CAS
INote91
(Note10)
Row address setup time before RAS
I REF
I RP
I RAS
I CAS
I CPN
I CSH
I RSH
I CRP
I RCo
I ASR
90
120
60
30
120
60
-20
25
0
2
10000
00
60
100
150
75
35
150
75
-20
30
0
2
10000
00
75
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
I su (CA-CAS)
I h (RAS-RA)
I h (CAS-CA)
I h (RAS-CA)
Column address setup time before CAS
Row address hold time after ~
Column address hold time after CAS
Column address hold time after RAS
IASC
I RAH
I CAH
I AR
0
15
20
90
0 ns
20 ns
25 ns
95 ns
ITHL
I TLH
Note 5:
6:
Transition time
IT 3 35 3 35
- --
An initial pause of 500J,ls is required after power-up followed by any eight RAS or RAS/CAS cycles before proper device operation IS achieved.
The switching characteristics are defined as t THL =t TLH =5ns.
ns
7: Reference levels of input signals are VIH min. and VI L max, Reference levels for transition time are also between VI H and V, L.
8: Except for page-mode,
9: td(CAS-RAS) requirement is only applicable for RASJ~AS cycles preceeded by a CAS only cycle (i.e., For systems where CAS has not been decoded with RAS.)
10: Operation within the td (RAS-CAS) max limit insures that ta (RAS) max can be met. td (RAS-CAS)maX is specified reference point only:if
td (RAS-CAS) is greater than the specified td (RAS--CAS) max limit, then access time is controlled exclusivel,! by ta(CAS)·
Id (RAS-CAS)mrn = Ih (RAS-RA)mrn + 21 THL(t TLH) + I SU(CA-CAS)mln_
SWITCHING CHARACTERISTICS (Ta =0-70·C, Vc6=5V ± 10%, VSS=OV, unless Otherwise noted)
Read Cycle
Symbol
leA
Isu (R-CAS)
Ih (CAS-R)
Ih (RAS-R)
Idls (CAS)
la (CAS)
la (RAS)
Parameter
Read cycle time
Read setup time before CAS
Read hold time after CAS
Read hold time after RAS
Output disable time
CAS access time
RAS access time
Alternative
Symbol
INote 111
INote 111
INote 121
INote 131
INote 141
I RC
I RCS
I RCH
I RRH
IOFF
I CAC
I RAC
M5K4164ANP-12
Limits
Min Max
220
0
0
10
0 35
60
120
M5K4164ANP-15
Limits
Min Max
260
0
0
20
0 40
75
150
No.te 11:
Note 12:
Note 13:
Note 14:
Either th (RAS-R) or th (CAS-R) must be satisfied for a read cycle.
tdis (CAS)maX defines the time at which the output 'achieves the open circuit condition and is not reference to VOH or VOL
This is the value when td (RAS-CAS)~ td (RAS-CAS)max. Test conditions; Load =:= 2T TL, Cl ==- 100pF
This is the value when td (RAS-CAS)< td (RAS-CAS)max. When td (RAS·CAS)~td (RAS-CAS)max. ta (RAS) will increase by the amount that
td (RAS-CAS) exceeds the value shown. Test conditions; Load = 2T TL. CL =: 100pF
Write Cycle
Unit
ns
ns
ns
ns
ns
ns
ns
Symbol
Parameter
lew
Isu (W-CAS)
Ih (CAS-W)
Ih (RAS-W)
Ih (W-RAS)
Ih (W-CAS)
Iw(W)
Isu (O-CAS)
Ih (CAS-D)
Ih (RAS-o)
Write cycle time
Write setup time before CAS
Write hofd time after CAS
Write hold time after RAS
RAS hold time after write
CAS hold time after write
Write pulse width
Data-in setup time before CAS
rnData-in hold time after
Data-in hold time after RAS
Alternative
Symbol
INote 171_
I RC
Iwcs
IWCH
IWCR
IRWL
ICWL
Iwp
lOS
IDH
loHR
M5K4164ANP-12
Limits
Min Max
220
-5
40
90
40
40
40
0
40
90
M5K4164ANP-15
Limits
Min
260
-10
Max
45
95
45
45
45
0
45
95
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2-18
• MITSUBISHI
;'ELECTRIC
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| M5K4164ANP-12 | The function is 64K-Bit DRAM. Mitsubishi | |
| M5K4164ANP-15 | The function is 64K-Bit DRAM. Mitsubishi | |
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