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M5K4164AP-15 fiches techniques PDF

Mitsubishi - 64K-Bit DRAM

Numéro de référence M5K4164AP-15
Description 64K-Bit DRAM
Fabricant Mitsubishi 
Logo Mitsubishi 





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M5K4164AP-15 fiche technique
MITSUBISHI LSI.
M5K4164AP-12, -15
65 536·BIT (65 536·WORD BY 1.BIT) DYNAMIC RAM
DESCRIPTION
This is a family of 65 536-word by l-bit dynamic RAMs,
fabricated with the high performance N-channel silicongate
MOS process, and is ideal for large-capacity memory
systems where high speed, low power dissipation, and low
costs are essential. The use of double-layer polysilicon
process technology and a single-transistor dynamic storage
cell privide high circuit density at reduced costs, and the
use of dynamic circuitry including sense amplifiers assures
low power dissipation_ Multiplexed address inputs permit
both a reduction in pins to the standard 16-pin package
configuration and an increase in system densities_ The
M5K4164AP operates on a 5V power supply using the
on-chip substrate bias generator_
PIN CONFIGURATION (TOP VIEW)
REFRESH INPUT REF
DATA INPUT
WRITE
CONTROL INPUT
ROW ADDRESS
STROBE INPUT
ADDRESS INPUTS
(WI Vee
Vss (OV)
15 ... CAS ~?~g~EN 1~~8fESS
I• ... Q DATA OUTPUT
ADDRESS INPUTS
FEATURES
• High speed
Type name
M5K4164AP-12
M5K4164AP-15
Access lime
~max I
(nsl
120
150
Cycle time
(min)
(ns)
220
260
Power diSSipation
(typ)
(mW)
175
150
• Single 5V±10%-supply
• Low standby power dissipation:
22mW (max)
• Low operating power dissipation: 300mW (max)
• Unlatched output enables two-dimensional chip selec-
tion and extended page boundary
• Early-write operation gives common 1/0 capability
• Read-modify-write, RAS-only refresh, and page-mode
capabilities
• All input terminals have low input capaciatance and are
directly TTL-compatible
Outline 16P4
• Output is three-state and directly TTL-compatible
• 128 refresh cycles every 2ms
(16K dynamic RAMs M5K4116P, S compatible)
• CAS controlled output allows hidden refresh
• Output data can be held infinitely by CAS
• Pin 1 controls automatic- and Self-refresh mode_
• Interchangeable with Fujitsu MB8265A and Motorola's
MCM6664 in pin configuration
APPLICATION
• Main memory unit for computers
BLOCK DIAGRAM
DATA INPUT
WRITE CONTROL INPUT
COLLUMN ADDRESS
STROBE INPUT
ROW ADDRESS
STROBE INPUT
ADDRESS INPUTS
COLUMN DECDDER
MEMORY CELL
164 ROWS X 256 COLLUMNS
SENSE REFRESH AMPLIFIER
MEMORY CELL
(64 ROWS x 256 COLUMNSI
COLUMN DECODER
MEMORY CELL
(64 ROWS x 256 COLUMNSI
SENSE REFRESH AMPLIFIER
(64 ROMWESMXOR2Y56CCEOLLLUMNSI
COLUMN DECODER
Vee (5V)
Vss (OV)
f-
12 14 Q DATA OUTPUT
f-
JoOJ
• . MITSUBISHI
;"ELECTRIC
2-3

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