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PDF SAM9G46 Data sheet ( Hoja de datos )
| Número de pieza | SAM9G46 | |
| Descripción | SMART ARM-based Embedded MPU | |
| Fabricantes | ATMEL Corporation | |
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SAM9G46
Atmel | SMART ARM-based Embedded MPU
DATASHEET
Description
The Atmel® | SMART ARM926EJ-S™-based SAM9G46 embedded
microprocessor unit (eMPU) features the frequently requested combination of
user interface functionality and high data rate connectivity, including LCD
controller, resistive touchscreen, camera interface, audio, Ethernet 10/100 and
high speed USB and SDIO. With the processor running at 400 MHz and multiple
100+ Mbps data rate peripherals, the SAM9G46 provides adequate performance
and bandwidth to the network or local storage media.
The SAM9G46 eMPU supports DDR2 and NAND Flash memory interfaces for
program and data storage. An internal 133 MHz multi-layer bus architecture
associated with 39 DMA channels, a dual external bus interface and distributed
memory including a 64-Kbyte SRAM that can be configured as a tightly coupled
memory (TCM) sustains the high bandwidth required by the processor and the
high speed peripherals.
On-chip hardware accelerators with DMA support enable high-speed data
encryption and authentication of the transferred data or application. Supported
standards are up to 256-bit AES, FIPS PUB 46-3 compliant TDES and FIPS
Publication 180-2 compliant SHA1 and SHA256. A True Random Number
Generator is embedded for key generation and exchange protocols.
The I/Os support 1.8V or 3.3V operation, which are independently configurable for
the memory interface and peripheral I/Os. This feature completely eliminates the
need for any external level shifters. In addition it supports 0.8 mm ball pitch
package for low cost PCB manufacturing.
The SAM9G46 power management controller features efficient clock gating and a
battery backup section minimizing power consumption in active and standby
modes.
Atmel-11028G-ATARM-SAM9G46-Datasheet_08-Dec-15
1 page  
Table 2-1. Signal Description List (Continued)
Signal Name
Function
Active Reference
Type Level Voltage Comments
Shutdown, Wakeup Logic
SHDN
Shutdown Control
Output
VDDBU
Driven at 0V only.
0: The device is in backup mode.
1: The device is running (not in
backup mode).
WKUP
Wake-up Input
Input
VDDBU Accepts between 0V and VDDBU
ICE and JTAG
TCK
Test Clock
Input
VDDIOP0 No pull-up resistor, Schmitt trigger
TDI Test Data In
Input
VDDIOP0 No pull-up resistor, Schmitt trigger
TDO
Test Data Out
Output
VDDIOP0
TMS
Test Mode Select
Input
VDDIOP0 No pull-up resistor, Schmitt trigger
JTAGSEL
JTAG Selection
Input
VDDBU Pull-down resistor (15 kΩ)
RTCK
Return Test Clock
Output
VDDIOP0
Reset/Test
NRST
Microcontroller Reset (2)
Open drain output.
I/O Low VDDIOP0 Pull-up resistor (100 kΩ), Schmitt
trigger.
TST
Test Mode Select
Input
VDDBU
Pull-down resistor (15 kΩ),
Schmitt trigger
NTRST
Test Reset Signal
Input
VDDIOP0
Pull-up resistor (100 kΩ),
Schmitt trigger
BMS
Boot Mode Select
Input
VDDIOP0
Must be connected to GND or
VDDIOP0
DRXD
DTXD
Debug Receive Data
Debug Transmit Data
Debug Unit - DBGU
Input
Output
(1)
(1)
Advanced Interrupt Controller - AIC
IRQ
External Interrupt Input
Input
(1)
FIQ
Fast Interrupt Input
Input
(1)
PA0–PA31
PIO Controller - PIOA / PIOB / PIOC / PIOD / PIOE
Parallel IO Controller A
I/O (1)
PB0–PB31
PC0–PC31
PD0–PD31
Parallel IO Controller B
Parallel IO Controller C
Parallel IO Controller D
I/O (1)
I/O
(1) Pulled-up input at reset
(100 kΩ)(3), Schmitt trigger
I/O (1)
PE0–PE31
Parallel IO Controller E
I/O (1)
SAM9G46 Series [DATASHEET]
Atmel-11028G-ATARM-SAM9G46-Datasheet_08-Dec-15
5
5 Page 
3. Package and Pinout
The SAM9G46 is delivered in a 324-ball TFBGA Green-compliant package.
3.1 324-ball TFBGA Package Outline
Figure 3-1 shows the orientation of the 324-ball TFBGA package.
A detailed mechanical description is given in Section 49. “Mechanical Characteristics”.
Figure 3-1.
Orientation of the 324-ball TFBGA Package
Bottom View
V
U
T
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
3.2 324-ball TFBGA Package Pinout
Table 3-1. SAM9G46 Pinout for 324-ball BGA Package
Pin Signal Name
Pin Signal Name
A1 PC27
E10 NANDWE
A2 PC28
E11 DQS1
A3 PC25
E12 D13
A4 PC20
E13 D11
A5 PC12
E14 A4
A6 PC7
E15 A8
A7 PC5
E16 A9
A8 PC0
E17 A7
A9 NWR3/NBS3
E18 VDDCORE
A10 NCS0
F1 PD22
A11 DQS0
F2 PD24
A12 RAS
F3 SHDN
A13 SDCK
F4 PE1
A14 NSDCK
F5 PE3
A15 D7
F6 VDDIOM1
A16 DDR_VREF
F7 PC19
Pin Signal Name
K1 PE21
K2 PE23
K3 PE26
K4 PE22
K5 PE24
K6 PE25
K7 PE27
K8 PE28
K9 VDDIOP0
K10 VDDIOP0
K11 GNDIOM
K12 GNDIOM
K13 VDDIOM0
K14 DDR_A7
K15 DDR_A8
K16 DDR_A9
Pin Signal Name
P10 TMS
P11 VDDPLLA
P12 PB20
P13 PB31
P14 DDR_D7
P15 DDR_D3
P16 DDR_D4
P17 DDR_D5
P18 DDR_D10
R1 PA18
R2 PA20
R3 PA24
R4 PA30
R5 PB4
R6 PB13
R7 PD0
SAM9G46 Series [DATASHEET]
Atmel-11028G-ATARM-SAM9G46-Datasheet_08-Dec-15
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet SAM9G46.PDF ] | |
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