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PDF C8051F961 Data sheet ( Hoja de datos )
| Número de pieza | C8051F961 | |
| Descripción | Ultra Low Power 128K LCD MCU | |
| Fabricantes | Silicon Laboratories | |
| Logotipo |  |
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C8051F96x
Ultra Low Power 128K, LCD MCU Family
Ultra Low Power Consumption at 3.6 V
- 130 µA/MHz Low-Power Active mode with dc-dc
enabled
- 120 nA sleep current w/ data retention; POR monitor
enabled
- 450 nA sleep mode with SmaRTClock
(internal LFO)
- 600 nA sleep mode with SmaRTClock (ext. crystal)
- 2 µs wakeup time; 1.5 µA analog settling time
12-Bit; 16 Ch. Analog-to-Digital Converter
- Up to 75 ksps (12-bit mode) or 300 ksps
(10-bit mode)
- External pin or internal VREF (no ext cap required)
- On-chip voltage reference; 0.5x gain allows measur-
ing voltages up to twice the reference voltage
- Autonomous burst mode with 16-bit auto-averaging
accumulator
- Integrated temperature sensor
Two Low Current Comparators
- Programmable hysteresis and response time
- Configurable as wake-up or reset source
Internal 6-Bit Current Reference
- Up to ±500 µA; source and sink capability
- Enhanced resolution via PWM interpolation
Integrated LCD Controller
- Supports up to 128 segments (32x4)
- LCD controller consumes only 400 nA for
32-segment static display
- Integrated charge pump for contrast control
Metering-Specific Peripherals
- DC-DC buck converter allows dynamic voltage
scaling for maximum efficiency (250 mW output)
- Sleep-mode pulse accumulator with programmable
switch, de-bounce and pull-up control; interfaces
directly to metering sensor
- Data Packet Processing Engine (DPPE) includes
hardware AES, DMA, CRC and encoding blocks for
acceleration of wireless protocols
High-Speed 8051 µC Core
- Pipelined instruction architecture; executes 70% of
instructions in 1 or 2 system clocks
Memory
- Up to 128 kB Flash; In-system programmable; Full
read/write/erase functionality over supply range
- Up to 8 kB internal data RAM
Digital Peripherals
- 57 or 34 port I/O; All 5 V tolerant with high sink
current and programmable drive strength
- Hardware SMBus™ (I2C™ Compatible), 2 x SPI™,
and UART serial ports available concurrently
- Four general purpose 16-bit counter/timers
- Programmable 16-bit counter/timer array with six
capture/compare modules and watchdog timer
Clock Sources
- Precision Internal oscillator: 24.5 MHz, 2% accuracy
supports UART operation; spread-spectrum mode
for reduced EMI
- Low power internal oscillator: 20 MHz
- External oscillator: Crystal, RC, C, or CMOS Clock
- SmaRTClock oscillator: 32 kHz Crystal or 16.4 kHz
internal LFO
On-Chip Debug
- On-chip debug circuitry facilitates full-speed, non-
intrusive in-system debug (no emulator required)
- Provides 4 breakpoints, single stepping
Packages
- 76-pin DQFN (6 x 6 mm)
- 40-pin QFN (6 x 6 mm)
- 80-pin TQFP (12 x 12 mm)
Temperature Range: –40 to +85 °C
C2CK/RST
VBAT
VDC
VBATDC
IND
GNDDC
CAP
GND
Power On
Reset/PMU
Wake
Reset
Debug /
Programming
Hardware
CIP-51 8051
Controller Core
128k Byte ISP Flash
Program Memory
256 Byte SRAM
8092 Byte XRAM
C2D
VBAT
VDD
VREG
Analog
Power
Digital
Power
DC/DC Buck
Converter
Precision
24.5 MHz
Oscillator
DMA
CRC
Engine
AES
Engine
Encoder
SYSCLK
LCD Charge
Pump
Low Power
20 MHz
Oscillator
XTAL1
XTAL2
External
Oscillator
Circuit
XTAL3
XTAL4
Enhanced
smaRTClock
Oscillator
System Clock
Configuration
SFR
Bus
Port I/O Configuration
Digital Peripherals
UART
Timers
0, 1, 2, 3
PCA/WDT
SMBus
Priority
Crossbar
Decoder
SPI 0
SPI 1
(DMA Enabled)
Crossbar Control
LCD (up to 4x32)
EMIF
Pulse Counter
Analog Peripherals
Internal External
VREF VREF
12-bit
75ksps
ADC
A
M
U
X
VDD
VREF
Temp
Sensor
GND
CP0, CP0A +
-
CP1, CP1A +
-
Comparators
Port 0
Drivers
Port 1
Drivers
Port 2
Drivers
P3-6
Drivers
P7
Driver
P0.0/VREF
P0.1/AGND
P0.2/XTAL1
P0.3/XTAL2
P0.4/TX
P0.5/RX
P0.6/CNVSTR
P0.7
P1.0/PC0
P1.1/PC1
P1.2/XTAL3
P1.3/XTAL4
P1.4
P1.5/INT5
P1.6/INT6
P1.7
P2.0/SCK1
P2.1/MISO1
P2.2/MOSI1
P2.3/NSS1
P2.4
P2.5
P2.6
P2.7
32
P3.0...P6.7
16
P7.0/C2D
Rev. 1.0 7/13
Copyright © 2013 by Silicon Laboratories
C8051F96x
1 page  
C8051F96x
11.2.1. DMA0 Memory Access Arbitration ........................................................ 148
11.2.2. DMA0 Channel Arbitration .................................................................... 148
11.3. DMA0 Operation in Low Power Modes ......................................................... 148
11.4. Transfer Configuration................................................................................... 149
12. Cyclic Redundancy Check Unit (CRC0)............................................................. 160
12.1. 16-bit CRC Algorithm..................................................................................... 160
12.3. Preparing for a CRC Calculation ................................................................... 163
12.4. Performing a CRC Calculation ...................................................................... 163
12.5. Accessing the CRC0 Result .......................................................................... 163
12.6. CRC0 Bit Reverse Feature............................................................................ 167
13. DMA-Enabled Cyclic Redundancy Check Module (CRC1)............................... 168
13.1. Polynomial Specification................................................................................ 168
13.2. Endianness.................................................................................................... 169
13.3. CRC Seed Value ........................................................................................... 170
13.4. Inverting the Final Value................................................................................ 170
13.5. Flipping the Final Value ................................................................................. 170
13.6. Using CRC1 with SFR Access ...................................................................... 171
13.7. Using the CRC1 module with the DMA ......................................................... 171
14. Advanced Encryption Standard (AES) Peripheral ............................................ 175
14.1. Hardware Description .................................................................................... 176
14.1.1. AES Encryption/Decryption Core .......................................................... 177
14.1.2. Data SFRs............................................................................................. 177
14.1.3. Configuration sfrs .................................................................................. 178
14.1.4. Input Multiplexer.................................................................................... 178
14.1.5. Output Multiplexer ................................................................................. 178
14.1.6. Internal State Machine .......................................................................... 178
14.2. Key Inversion................................................................................................. 179
14.2.1. Key Inversion using DMA...................................................................... 180
14.2.2. Key Inversion using SFRs..................................................................... 181
14.2.3. Extended Key Output Byte Order.......................................................... 182
14.2.4. Using the DMA to unwrap the extended Key ........................................ 183
14.3. AES Block Cipher .......................................................................................... 184
14.4. AES Block Cipher Data Flow......................................................................... 185
14.4.1. AES Block Cipher Encryption using DMA ............................................. 186
14.4.2. AES Block Cipher Encryption using SFRs ............................................ 187
14.5. AES Block Cipher Decryption........................................................................ 188
14.5.1. AES Block Cipher Decryption using DMA............................................. 188
14.5.2. AES Block Cipher Decryption using SFRs............................................ 189
14.6. Block Cipher Modes ...................................................................................... 190
14.6.1. Cipher Block Chaining Mode................................................................. 190
14.6.2. CBC Encryption Initialization Vector Location....................................... 192
14.6.3. CBC Encryption using DMA .................................................................. 192
14.6.4. CBC Decryption .................................................................................... 195
14.6.5. Counter Mode ....................................................................................... 198
14.6.6. CTR Encryption using DMA .................................................................. 200
Rev. 1.0
4
5 Page 
C8051F96x
List of Figures
Figure 1.1. C8051F960 Block Diagram ................................................................... 23
Figure 1.2. C8051F961 Block Diagram ................................................................... 23
Figure 1.3. C8051F962 Block Diagram ................................................................... 24
Figure 1.4. C8051F963 Block Diagram ................................................................... 24
Figure 1.5. C8051F964 Block Diagram ................................................................... 25
Figure 1.6. C8051F965 Block Diagram ................................................................... 25
Figure 1.7. C8051F966 Block Diagram ................................................................... 26
Figure 1.8. C8051F967 Block Diagram ................................................................... 26
Figure 1.9. C8051F968 Block Diagram ................................................................... 27
Figure 1.10. C8051F969 Block Diagram ................................................................. 27
Figure 1.11. Port I/O Functional Block Diagram ...................................................... 29
Figure 1.12. PCA Block Diagram ............................................................................. 30
Figure 1.13. ADC0 Functional Block Diagram ......................................................... 31
Figure 1.14. ADC0 Multiplexer Block Diagram ........................................................ 32
Figure 1.15. Comparator 0 Functional Block Diagram ............................................ 33
Figure 1.16. Comparator 1 Functional Block Diagram ............................................ 33
Figure 3.1. DQFN-76 Pinout Diagram (Top View) ................................................... 43
Figure 3.2. QFN-40 Pinout Diagram (Top View) ..................................................... 44
Figure 3.3. TQFP-80 Pinout Diagram (Top View) ................................................... 45
Figure 3.4. DQFN-76 Package Drawing .................................................................. 46
Figure 3.5. DQFN-76 Land Pattern ......................................................................... 47
Figure 3.6. Recomended Inner Via Placement ........................................................ 49
Figure 3.7. Typical QFN-40 Package Drawing ........................................................ 50
Figure 3.8. QFN-40 Landing Diagram ..................................................................... 51
Figure 3.9. TQFP-80 Package Drawing .................................................................. 52
Figure 3.10. TQFP80 Landing Diagram .................................................................. 54
Figure 4.1. Frequency Sensitivity (External CMOS Clock, 25°C) ............................ 64
Figure 4.2. Typical VOH Curves, 1.8–3.6 V ............................................................ 66
Figure 4.3. Typical VOL Curves, 1.8–3.6 V ............................................................. 67
Figure 5.1. ADC0 Functional Block Diagram ........................................................... 78
Figure 5.2. 10-Bit ADC Track and Conversion Example Timing
(BURSTEN = 0) .................................................................................... 81
Figure 5.3. Burst Mode Tracking Example with Repeat Count Set to 4 .................. 82
Figure 5.4. ADC0 Equivalent Input Circuits ............................................................. 83
Figure 5.5. ADC Window Compare Example: Right-Justified
Single-Ended Data ................................................................................ 94
Figure 5.6. ADC Window Compare Example: Left-Justified
Single-Ended Data ................................................................................ 94
Figure 5.7. ADC0 Multiplexer Block Diagram .......................................................... 95
Figure 5.8. Temperature Sensor Transfer Function ................................................ 97
Figure 5.9. Temperature Sensor Error with 1-Point Calibration
(VREF = 1.68 V) ..................................................................................... 98
Figure 5.10. Voltage Reference Functional Block Diagram ................................... 100
Rev. 1.0
10
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet C8051F961.PDF ] | |
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