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PDF IMX51 Data sheet ( Hoja de datos )
| Número de pieza | IMX51 | |
| Descripción | Applications Processors | |
| Fabricantes | Freescale Semiconductor | |
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Freescale Semiconductor
Data Sheet: Technical Data
Document Number: IMX51CEC
Rev. 6, 10/2012
IMX51
i.MX51 Applications
Processors for Consumer and
Industrial Products
Package Information
Plastic Package
Case 2058 13 x 13 mm, 0.5 mm pitch
Case 2017 19 x 19 mm, 0.8 mm pitch
Ordering Information
See Table 1 on page 3 for ordering information.
1 Introduction
The i.MX51 multimedia applications processors
represent Freescale Semiconductor’s latest addition to a
growing family of multimedia-focused products that
offer high performance processing and are optimized for
lowest power consumption.
The i.MX51 processors feature Freescale’s advanced and
power-efficient implementation of the ARM
Cortex™-A8 core, which operates at speeds as high as
800 MHz. Up to 200 MHz DDR2 and mobile DDR
DRAM clock rates are supported. These devices are
suitable for applications such as the following:
• Netbooks (web tablets)
• Nettops (Internet desktop devices)
• Mobile Internet devices (MID)
• Portable media players (PMP)
• Portable navigation devices (PND)
• High-end PDAs
• Gaming consoles
• Automotive navigation and entertainment (see
automotive data sheet, IMX51AEC)
1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 3
1.2. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2. Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.1. Special Signal Considerations . . . . . . . . . . . . . . . 12
3. IOMUX Configuration for Boot Media . . . . . . . . . . . . . . . 14
3.1. NAND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.2. SD/MMC IOMUX Pin Configuration . . . . . . . . . . . 15
3.3. I2C IOMUX Pin Configuration . . . . . . . . . . . . . . . . 15
3.4. eCSPI/CSPI IOMUX Pin Configuration . . . . . . . . 16
3.5. Wireless External Interface Module (WEIM) . . . . 16
3.6. UART IOMUX Pin Configuration . . . . . . . . . . . . . 16
3.7. USB-OTG IOMUX Pin Configuration . . . . . . . . . . 16
4. Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 17
4.1. Chip-Level Conditions . . . . . . . . . . . . . . . . . . . . . 17
4.2. Supply Power-Up/Power-Down Requirements and
Restrictions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.3. I/O DC Parameters . . . . . . . . . . . . . . . . . . . . . . . . 24
4.4. Output Buffer Impedance Characteristics . . . . . . 31
4.5. I/O AC Parameters . . . . . . . . . . . . . . . . . . . . . . . . 35
4.6. Module Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
4.7. External Peripheral Interfaces . . . . . . . . . . . . . . . 74
5. Package Information and Contact Assignments . . . . . 153
5.1. 13 x 13 mm Package Information . . . . . . . . . . . . 153
5.2. 19 x 19 mm Package Information . . . . . . . . . . . . 173
5.3. 13 × 13 mm, 0.5 Pitch Ball Map . . . . . . . . . . . . . 191
5.4. 19 x 19 mm, 0.8 Pitch Ball Map . . . . . . . . . . . . . 195
6. Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
© 2012 Freescale Semiconductor, Inc. All rights reserved.
1 page  
Features
2 Features
The i.MX51 processor contains a large number of digital and analog modules that are described in Table 2.
Table 2. i.MX51 Digital and Analog Modules
Block
Mnemonic
Block Name Subsystem
Brief Description
1-WIRE
1-Wire
Interface
ARM
ARM
Cortex™-A8 Cortex™-A8
Platform
Audio Audio
Subsystem Subsystem
Connectivity
Peripherals
ARM
Multimedia
Peripherals
1-Wire support provided for interfacing with an on-board EEPROM, and smart
battery interfaces, for example: Dallas DS2502.
The ARM Cortex™-A8 Core Platform consists of the ARM Cortex™-A8
processor version r2p5 (with TrustZone) and its essential sub-blocks. It contains
the Level 2 Cache Controller, 32 Kbyte L1 instruction cache, 32 Kbyte L1 data
cache, and a 256 Kbyte L2 cache. The platform also contains an Event Monitor
and Debug modules. It also has a NEON co-processor with SIMD media
processing architecture, register file with 32 × 64-bit general-purpose registers,
an Integer execute pipeline (ALU, Shift, MAC), dual, single-precision floating
point execute pipeline (FADD, FMUL), load/store and permute pipeline and a
Non-Pipelined Vector Floating Point (VFP) co-processor (VFPv3).
The elements of the audio subsystem are three Synchronous Serial Interfaces
(SSI1-3), a Digital Audio Mux (AUDMUX), and Digital Audio Out (SPDIF TX).
See the specific interface listings in this table.
AUDMUX
CCM
GPC
SRC
Digital Audio Multimedia
Mux Peripherals
The AUDMUX is a programmable interconnect for voice, audio, and
synchronous data routing between host serial interfaces (for example, SSI1,
SSI2, and SSI3) and peripheral serial interfaces (audio and voice codecs). The
AUDMUX has seven ports (three internal and four external) with identical
functionality and programming models. A desired connectivity is achieved by
configuring two or more AUDMUX ports.
Clock Control Clocks,
These modules are responsible for clock and reset distribution in the system,
Module
Resets, and and also for system power management. The modules include three PLLs and
Global Power Power Control a Frequency Pre-Multiplier (FPM).
Controller
System Reset
Controller
CSPI-1,
eCSPI-2
eCSPI-3
Configurable
SPI,
Enhanced
CSPI
Connectivity
Peripherals
Full-duplex enhanced Synchronous Serial Interface, with data rate up to
66.5 Mbit/s (for eCSPI, master mode). It is configurable to support Master/Slave
modes, four chip selects to support multiple peripherals.
CSU
Central
Security
Security Unit
The Central Security Unit (CSU) is responsible for setting comprehensive
security policy within the i.MX51 platform, and for sharing security information
between the various security modules. The Security Control Registers (SCR) of
the CSU are set during boot time by the High Assurance Boot (HAB) code and
are locked to prevent further writing.
Debug
System
Debug
System
System
Control
The Debug System provides real-time trace debug capability of both instructions
and data. It supports a trace protocol that is an integral part of the ARM Real
Time Debug solution (RealView). Real-time tracing is controlled by specifying a
set of triggering and filtering resources, which include address and data
comparators, cross-system triggers, counters, and sequencers.
i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 6
Freescale Semiconductor
5
5 Page 
Features
Table 2. i.MX51 Digital and Analog Modules (continued)
Block
Mnemonic
Block Name Subsystem
Brief Description
UART-1
UART-2
UART-3
USB
VPU
WDOG-1
WDOG-2
(TZ)
XTALOSC
UART
Interface
Connectivity
Peripherals
USB 2.0
High-Speed
OTG and 3x
Hosts
Video
Processing
Unit
Connectivity
Peripherals
Multimedia
Peripherals
Watch Dog
Timer
Peripherals
Watch Dog Timer
(TrustZone) Peripherals
Crystal
Clocking
Oscillator I/F
Each of the UART modules supports the following serial data transmit/receive
protocols and configurations:
• 7 or 8 bit data words, 1 or 2 stop bits, programmable parity (even, odd, or
none)
• Programmable baud rates up to 4 MHz. This is a higher max baud rate relative
to the 1.875 MHz, which is stated by the TIA/EIA-232-F standard and
previous Freescale UART modules.
• 32-byte FIFO on Tx and 32 half-word FIFO on Rx supporting auto-baud
• IrDA 1.0 support (up to SIR speed of 115200 bps)
• Option to operate as 8-pins full UART, DCE, or DTE
USB-OTG contains one high-speed OTG module, which is internally connected
to the on-chip HS USB PHY. There are an additional three high-speed host
modules that require external USB PHYs.
A high-performing video processing unit (VPU), which covers many SD-level
video decoders and SD-level encoders as a multi-standard video codec engine
as well as several important video processing such as rotation and mirroring.
VPU Features:
• MPEG-4 decode: 720p, 30 fps, simple profile and advanced simple profile
• MPEG-4 encode: D1, 25/30 fps, simple profile
• H.263 decode: 720p, 30 fps, profile 3
• H.263 encode: D1, 25/30 fps, profile 3
• H.264 decode: 720p, 30 fps, baseline, main, and high profile
• H.264 encode: D1, 25/30 fps, baseline profile
• MPEG-2 decode: 720p, 30 fps, MP-ML
• MPEG-2 encode: D1, 25/30 fps, MP-ML (in software with partial acceleration
in hardware)
• VC-1 decode: 720p, 30 fps, simple, main, and advanced profile
• DivX decode: 720p, 30 fps versions 3, 4, and 5
• RV10 decode: 720p, 30 fps
• MJPEG decode: 32 Mpix/s
• MJPEG encode: 64 Mpix/s
The Watch Dog Timer supports two comparison points during each counting
period. Each of the comparison points is configurable to evoke an interrupt to the
ARM core, and a second point evokes an external event on the WDOG line.
The TrustZone Watchdog (TZ WDOG) timer module protects against TrustZone
starvation by providing a method of escaping normal mode and forcing a switch
to the TZ mode. TZ starvation is a situation where the normal OS prevents
switching to the TZ mode. This situation should be avoided, as it can
compromise the system’s security. Once the TZ WDOG module is activated, it
must be serviced by TZ software on a periodic basis. If servicing does not take
place, the timer times out. Upon a time-out, the TZ WDOG asserts a TZ mapped
interrupt that forces switching to the TZ mode. If it is still not served, the TZ
WDOG asserts a security violation signal to the CSU. The TZ WDOG module
cannot be programmed or deactivated by a normal mode SW.
The XTALOSC module allows connectivity to an external crystal.
i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 6
Freescale Semiconductor
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet IMX51.PDF ] | |
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