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PDF CAT515 Data sheet ( Hoja de datos )
| Número de pieza | CAT515 | |
| Descripción | 8-Bit Quad Digital POT with Independent Reference Inputs | |
| Fabricantes | Catalyst Semiconductor | |
| Logotipo |  |
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CAT515
8-Bit Quad Digital POT with Independent Reference Inputs
FEATURES
APPLICATIONS
s Output settings retained without power
s Independent Reference Inputs
s Output range includes both supply rails
s Programming voltage generated on-chip
s 4 independently addressable outputs
s Serial µP interface
s Single supply operation: 2.7V-5.5V
s Automated product calibration.
s Remote control adjustment of equipment
s Offset, gain and zero adjustments in Self-
Calibrating and Adaptive Control systems.
s Tamper-proof calibrations.
DESCRIPTION
The CAT515 is a quad 8-Bit Memory DAC designed as
an electronic replacement for mechanical potentiom-
eters and trim pots. Intended for final calibration of
products such as camcorders, fax machines and cellular
telephones on automated high volume production lines
and systems capable of self calibration, it is also well
suited for applications were equipment requiring peri-
odic adjustment is either difficult to access or located in
a hazardous environment.
The CAT515 offers 4 independently programmable DACs
each having its own reference inputs and each capable
of rail to rail output swing. Output settings, stored non-
volatile EEPROM memory, are not lost when the device
is powered down and are automatically reinstated when
power is returned. Each output can be dithered to test
new output values without effecting the stored settings
and stored settings can be read back without disturbing
the DAC’s output.
FUNCTIONAL DIAGRAM
VDD
3
Control of the CAT515 is accomplished with a simple 3
wire serial interface. A Chip Select pin allows several
CAT515's to share a common serial interface and com-
munications back to the host controller is via a single
serial data line thanks to the CAT515’s Tri-Stated Data
Output pin. A RDY/BSYoutput working in concert with
an internal low voltage detector signals proper operation
of EEPROM Erase/Write cycle.
The CAT515 operates from a single 3–5 volt power
supply. The high voltage required for EEPROM Erase/
Write operations is generated on-chip.
The CAT515 is available in the 0°C to 70°C Commercial
and –40°C to +85°C Industrial operating temperature
ranges and offered in 20-pin plastic DIP and Surface
mount packages.
PIN CONFIGURATION
RDY/BSY
5
PROG
9
PROGRAM
CONTROL
SERIAL DATA OUTPUT
EEPROM
LATCH
DAC 1
CLK
4
6
CS
DI 7
DATA
CONTROLLER
EEPROM
LATCH
DAC 2
EEPROM
LATCH
DAC 3
H.V.
CHARGE
PUMP
CAT515
EEPROM
LATCH
DAC 4
10
GND
8
DO
2
VREF H1
18
VOUT 1
11
VREF L1
1
VREF H2
17
VOUT 2
12
VREF L2
20
VREF H3
16
VOUT 3
13
VREF L3
19
VREF H4
15
VOUT 4
14
VREF L4
DIP Package (P)
SOIC Package (J)
VREF H4
VREF H1
DVD
CLK
RDY/BSY
CS
DI
DO
PROG
GND
1 20
2 19
3 18
4 17
5 CAT51516
6 15
7 14
8 13
9 12
10 11
VREF H3 VREF H4
VREF H4 VREF H1
VOUT1
DVD
VOUT2
CLK
VOUT3
VOUT4
RDY/BSY
CS
VREF L4
DI
VREF L3
DO
VREF L2
VREF L1
PROG
GND
1 20
2 19
3 18
4 17
5 16
CAT515
6 15
7 14
8 13
9 12
10 11
VREF H3
VREF H4
VOUT1
VOUT2
VOUT3
VOUT4
VREF L4
VREF L3
VREF L2
VREF L1
© 2000 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1
Doc. No. 25077-00 2/98 M-1
1 page  
CAT515
PIN DESCRIPTION
Pin Name
Function
1 VREFH2 Maximum DAC 2 output voltage
2 VREFH1 Maximum DAC 1 output voltage
3 VDD
Power supply positive
4 CLK
Clock input pin
5 RDY/BSY Ready/Busy output
6 CS
Chip select
7 DI
Serial data input pin
8 DO
Serial data output pin
9 PROG
EEPROM Programming Enable
Input
10 GND
Power supply ground
11 VREFL1
Minimum DAC 1 output voltage
12 VREFL2
Minimum DAC 2 output voltage
13 VREFL3
14 VREFL4
Minimum DAC 3 output voltage
Minimum DAC 4 output voltage
15 VOUT4
DAC 4 output
16 VOUT3
DAC 3 output
17 VOUT2
18 VOUT1
19 VREFH4
DAC 2 output
DAC 1 output
Maximum DAC 4 output voltage
20 VREFH3
Maximum DAC 3 output voltage
DAC addressing is as follows:
DAC OUTPUT
VOUT1
VOUT2
VOUT3
VOUT4
A0
0
1
0
1
A1
0
0
1
1
DEVICE OPERATION
The CAT515 is a quad 8-bit Digital to Analog Converter
(DAC) whose outputs can be programmed to any one of
256 individual voltage steps. Once programmed, these
output settings are retained in non-volatile EEPROM
memory and will not be lost when power is removed from
the chip. Upon power up the DACs return to the settings
stored in EEPROM memory. Each DAC can be written
to and read from independently without effecting the
output voltage during the read or write cycle. Each
output can also be adjusted without altering the stored
output setting, which is useful for testing new output
settings before storing them in memory.
DIGITAL INTERFACE
The CAT515 employs a standard 3 wire serial control
interface consisting of Clock (CLK), Chip Select (CS)
and Data In (DI) inputs. For all operations, address and
data are shifted in LSB first. In addition, all digital data
must be preceded by a logic “1” as a start bit. The DAC
address and data are clocked into the DI pin on the
clock’s rising edge. When sending multiple blocks of
information a minimum of two clock cycles is required
between the last block sent and the next start bit.
Multiple devices may share a common input data line by
selectively activating the CS control of the desired IC.
Data Outputs (DO) can also share a common line
because the DO pin is Tri-Stated and returns to a high
impedance when not in use.
5
CHIP SELECT
Chip Select (CS) enables and disables the CAT515’s
read and write operations. When CS is high data may be
read to or from the chip, and the Data Output (DO) pin is
active. Data loaded into the DAC control registers will
remain in effect until CS goes low. Bringing CS to a logic
low returns all DAC outputs to the settings stored in
EEPROM memory and switches DO to its high imped-
ance Tri-State mode.
Because CS functions like a reset the CS pin has been
desensitized with a 30 ns to 90 ns filter circuit to prevent
noise spikes from causing unwanted resets and the loss
of volatile data.
CLOCK
The CAT515’s clock controls both data flow in and out of
the IC and EEPROM memory cell programming. Serial
data is shifted into the DI pin and out of the DO pin on the
clock’s rising edge. While it is not necessary for the clock
to be running between data transfers, the clock must be
operating in order to write to EEPROM memory, even
though the data being saved may already be resident in
the DAC control register.
No clock is necessary upon system power-up. The
CAT515’s internal power-on reset circuitry loads data
from EEPROM to the DACs without using the external
clock.
Doc. No. 25077-00 2/98 M-1
5 Page 
CAT515
ORDERING INFORMATION
Prefix
Device #
Suffix
CAT 515
J
I -TE13
Optional
Company ID
Product
Number
Package
P: PDIP
J: SOIC
Tape & Reel
TE13: 2000/Reel
Temperature Range
Blank = Commercial (0˚C to +70˚C)
I = Industrial (-40˚C to +85˚C)
Notes:
(1) The device used in the above example is a CAT515JI-TE13 (SOIC, Industrial Temperature, Tape & Reel)
11 Doc. No. 25077-00 2/98 M-1
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet CAT515.PDF ] | |
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