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PDF CAT28LV65 Data sheet ( Hoja de datos )
| Número de pieza | CAT28LV65 | |
| Descripción | 64K-Bit CMOS PARALLEL E2PROM | |
| Fabricantes | Catalyst Semiconductor | |
| Logotipo |  |
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Preliminary
CAT28LV65
64K-Bit CMOS PARALLEL E2PROM
FEATURES
s 3.0V to 3.6V Supply
s Read Access Times:
– 250/300/350ns
s Low Power CMOS Dissipation:
– Active: 8 mA Max.
– Standby: 100 µA Max.
s Simple Write Operation:
– On-Chip Address and Data Latches
– Self-Timed Write Cycle with Auto-Clear
s Fast Write Cycle Time:
– 5ms Max.
s Commercial, Industrial and Automotive
Temperature Ranges
DESCRIPTION
The CAT28LV65 is a low voltage, low power, CMOS
parallel E2PROM organized as 8K x 8-bits. It requires a
simple interface for in-system programming. On-chip
address and data latches, self-timed write cycle with
auto-clear and VCC power up/down write protection
eliminate additional timing and protection hardware.
DATA Polling, RDY/BUSY and Toggle status bit signal
the start and end of the self-timed write cycle. Addition-
ally, the CAT28LV65 features hardware and software
write protection.
s CMOS and TTL Compatible I/O
s Automatic Page Write Operation:
– 1 to 32 Bytes in 5ms
– Page Load Timer
s End of Write Detection:
– Toggle Bit
– DATA Polling
– RDY/BUSY
s Hardware and Software Write Protection
s 100,000 Program/Erase Cycles
s 100 Year Data Retention
The CAT28LV65 is manufactured using Catalyst’s ad-
vanced CMOS floating gate technology. It is designed to
endure 100,000 program/erase cycles and has a data
retention of 100 years. The device is available in JEDEC
approved 28-pin DIP, 28-pin TSOP, 28-pin SOIC or 32-
pin PLCC packages.
BLOCK DIAGRAM
A5–A12
VCC
CE
OE
WE
A0–A4
RDY/BUSY
ADDR. BUFFER
& LATCHES
INADVERTENT
WRITE
PROTECTION
CONTROL
LOGIC
TIMER
ADDR. BUFFER
& LATCHES
ROW
DECODER
HIGH VOLTAGE
GENERATOR
DATA POLLING,
RDY/BUSY &
TOGGLE BIT
COLUMN
DECODER
8,192 x 8
E2PROM
ARRAY
32 BYTE PAGE
REGISTER
I/O BUFFERS
I/O0–I/O7
28LV65 F01
© 1998 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1
Doc. No. 25041-00 2/98
1 page  
Preliminary
Figure 1. A.C. Testing Input/Output Waveform(4)
VCC - 0.3 V
0.0 V
INPUT PULSE LEVELS
2.0 V
0.6 V
REFERENCE POINTS
Figure 2. A.C. Testing Load Circuit (example)
Vcc
DEVICE
UNDER
TEST
1. 3K
1.8 K
OUTPUT
CL= 100 pF
CAT28LV65
28LV65 F05
CL INCLUDES JIG CAPACITANCE
A.C. CHARACTERISTICS, Write Cycle
Vcc = 3.0V to 3.6V, unless otherwise specified.
28LV65 F07
Symbol
tWC
tAS
tAH
tCS
tCH
tCW(2)
tOES
tOEH
tWP(2)
tDS
tDH
tINIT(1)
tBLC(1)(3)
tRB
Parameter
Write Cycle Time
Address Setup Time
Address Hold Time
CE Setup Time
CE Hold Time
CE Pulse Time
OE Setup Time
OE Hold Time
WE Pulse Width
Data Setup Time
Data Hold Time
Write Inhibit Period After Power-up
Byte Load Cycle Time
WE Low to RDY/BSY Low
28LV65-25
Min. Max.
5
0
100
0
0
150
10
10
150
100
0
5 10
0.1 100
220
28LV65-30
Min. Max.
5
0
100
0
0
150
10
10
150
100
0
5 10
0.1 100
220
28LV65-35
Min. Max.
5
0
100
0
0
150
10
10
150
100
0
5 10
0.1 100
220
Units
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
µs
ns
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) A write pulse of less than 20ns duration will not initiate a write cycle.
(3) A timer of duration tBLC max. begins with every LOW to HIGH transition of WE. If allowed to time out, a page or byte write will begin;
however a transition from HIGH to LOW within tBLC max. stops the timer.
(4) Input rise and fall times (10% and 90%) < 10 ns.
5 Doc. No. 25041-00 2/98
5 Page | ||
| Páginas | Total 10 Páginas | |
| PDF Descargar | [ Datasheet CAT28LV65.PDF ] | |
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