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PDF CAT28HT256 Data sheet ( Hoja de datos )
| Número de pieza | CAT28HT256 | |
| Descripción | 256K-Bit CMOS PARALLEL E2PROM | |
| Fabricantes | Catalyst Semiconductor | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de CAT28HT256 (archivo pdf) en la parte inferior de esta página. Total 10 Páginas | ||
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Advanced
CAT28HT256
256K-Bit CMOS PARALLEL E2PROM
Extended Temperature: 170˚C
FEATURES
s Fast Read Access Times: 200/250 ns
s Low Power CMOS Dissipation:
–Active: 30 mA Max.
–Standby: 150 µA Max.
s Simple Write Operation:
–On-Chip Address and Data Latches
–Self-Timed Write Cycle with Auto-Clear
s Fast Write Cycle Time:
–10ms Max
s CMOS and TTL Compatible I/O
s Automatic Page Write Operation:
–1 to 64 Bytes in 10ms
–Page Load Timer
s End of Write Detection:
–Toggle Bit
–DATA Polling
s Hardware and Software Write Protection
s 100,000 Program/Erase Cycles
s 100 Year Data Retention
DESCRIPTION
The CAT28HT256 is a fast, low power, 5V-only CMOS
parallel E2PROM organized as 32K x 8-bits. It requires
a simple interface for in-system programming. On-chip
address and data latches, self-timed write cycle with
auto-clear and VCC power up/down write protection
eliminate additional timing and protection hardware.
DATA Polling and Toggle status bits signal the start and
end of the self-timed write cycle. Additionally, the
CAT28HT256 features hardware and software write
protection as well as an internal Error Correction Code
(ECC) for extremely high reliability.
The CAT28HT256 is manufactured using Catalyst’s
advanced CMOS floating gate technology. It is designed
to endure 100,000 program/erase cycles and has a data
retention of 100 years. The device is available in JEDEC
approved 28-pin Ceramic DIP package.
BLOCK DIAGRAM
A6–A14
ADDR. BUFFER
& LATCHES
VCC
CE
OE
WE
INADVERTENT
WRITE
PROTECTION
CONTROL
LOGIC
A0–A5
TIMER
ADDR. BUFFER
& LATCHES
ROW
DECODER
HIGH VOLTAGE
GENERATOR
DATA POLLING
AND
TOGGLE BIT
COLUMN
DECODER
32,768 x 8
E2PROM
ARRAY
64 BYTE PAGE
REGISTER
I/O BUFFERS
I/O0–I/O7
5096 FHD F02
© 1998 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
8-91
1 page  
Advanced
CAT28HT256
DEVICE OPERATION
Read
Data stored in the CAT28HT256 is transferred to the
data bus when WE is held high, and both OE and CE are
held low. The data bus is set to a high impedance state
when either CE or OE goes high. This 2-line control
architecture can be used to eliminate bus contention in
a system environment.
Byte Write
A write cycle is executed when both CE and WE are low,
and OE is high. Write cycles can be initiated using either
WE or CE, with the address input being latched on the
falling edge of WE or CE, whichever occurs last. Data,
conversely, is latched on the rising edge of WE or CE,
whichever occurs first. Once initiated, a byte write cycle
automatically erases the addressed byte and the new
data is written within 10 ms.
Figure 1. A.C. Testing Input/Output Waveform(1)
2.4 V
0.45 V
INPUT PULSE LEVELS
2.0 V
0.8 V
REFERENCE POINTS
Note:
(1) Input rise and fall times (10% and 90%) < 10 ns.
5096 FHD F03
Figure 2. A.C. Testing Load Circuit (example)
1.3V
1N914
DEVICE
UNDER
TEST
3.3K
OUT
CL = 100 pF
Figure 3. Read Cycle
ADDRESS
CE
OE
WE
DATA OUT
CL INCLUDES JIG CAPACITANCE
tRC
tCE
tOE
VIH
tLZ
HIGH-Z
tOLZ
tOH
DATA VALID
tAA
5096 FHD F04
tOHZ
tHZ
DATA VALID
8-95
Stock No. 21065-03 2/98
5 Page | ||
| Páginas | Total 10 Páginas | |
| PDF Descargar | [ Datasheet CAT28HT256.PDF ] | |
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