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PDF CAT28F512 Data sheet ( Hoja de datos )
| Número de pieza | CAT28F512 | |
| Descripción | 512K-Bit CMOS Flash Memory | |
| Fabricantes | Catalyst Semiconductor | |
| Logotipo |  |
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CAT28F512
512K-Bit CMOS Flash Memory
Licensed Intel
second source
FEATURES
s Fast Read Access Time: 90/120/150 ns
s Low Power CMOS Dissipation:
–Active: 30 mA max (CMOS/TTL levels)
–Standby: 1 mA max (TTL levels)
–Standby: 100 µA max (CMOS levels)
s High Speed Programming:
–10 µs per byte
–1 Sec Typ Chip Program
s 12.0V ± 5% Programming and Erase Voltage
s Electronic Signature
DESCRIPTION
The CAT28F512 is a high speed 64K x 8-bit electrically
erasable and reprogrammable Flash memory ideally
suited for applications requiring in-system or after-sale
code updates. Electrical erasure of the full memory
contents is achieved typically within 0.5 second.
It is pin and Read timing compatible with standard
EPROM and E2PROM devices. Programming and
Erase are performed through an operation and verify
algorithm. The instructions are input via the I/O bus,
s Commercial, Industrial and Automotive
Temperature Ranges
s Stop Timer for Program/Erase
s On-Chip Address and Data Latches
s JEDEC Standard Pinouts:
–32-pin DIP
–32-pin PLCC
–32-pin TSOP ( 8 x 20)
s 100,000 Program/Erase Cycles
s 10 Year Data Retention
using a two write cycle scheme. Address and Data are
latched to free the I/O bus and address bus during the
write operation.
The CAT28F512 is manufactured using Catalyst’s ad-
vanced CMOS floating gate technology. It is designed
to endure 100,000 program/erase cycles and has a data
retention of 10 years. The device is available in JEDEC
approved 32-pin plastic DIP, 32-pin PLCC or 32-pin
TSOP packages.
BLOCK DIAGRAM
ERASE VOLTAGE
SWITCH
I/O0–I/O7
I/O BUFFERS
WE
CE
OE
A0–A15
COMMAND
REGISTER
PROGRAM VOLTAGE
SWITCH
CE, OE LOGIC
DATA SENSE
LATCH AMP
VOLTAGE VERIFY
SWITCH
Y-DECODER
X-DECODER
Y-GATING
524,288 BIT
MEMORY
ARRAY
28F512 F02
© 1998 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1
Doc. No. 25042-00 2/98 F-1
1 page  
Preliminary
CAT28F512
SUPPLY CHARACTERISTICS
Symbol
Parameter
VCC VCC Supply Voltage
VPPL
VPP During Read Operations
VPPH
VPP During Read/Erase/Program
A.C. CHARACTERISTICS, Read Operation
VCC = +5V ±10%, unless otherwise specified.
Limits
Min Max.
4.5 5.5
0 6.5
11.4 12.6
Unit
V
V
V
JEDEC Standard
Symbol Symbol
Parameter
tAVAV tRC Read Cycle Time
tELQV tCE CE Access Time
tAVQV
tACC Address Access Time
tGLQV tOE OE Access Time
tAXQX tOH Output Hold from Address OE/CE Change
tGLQX
tOLZ(1)(6) OE to Output in Low-Z
tELQX
tLZ(1)(6) CE to Output in Low-Z
tGHQZ
tDF(1)(2) OE High to Output High-Z
tEHQZ
tDF(1)(2) CE High to Output High-Z
tWHGL(1) -
Write Recovery Time Before Read
28F512-90 28F512-12 28F512-15
Min. Max. Min. Max. Min. Max. Unit
90 120 150 ns
90 120 150 ns
90 120 150 ns
35 50 55 ns
0 0 0 ns
0 0 0 ns
0 0 0 ns
20 30 35 ns
30 40 45 ns
6 6 6 µs
Figure 1. A.C. Testing Input/Output Waveform(3)(4)(5)
2.4 V
0.45 V
INPUT PULSE LEVELS
2.0 V
0.8 V
Figure 2. A.C. Testing Load Circuit (example)
1.3V
1N914
REFERENCE POINTS
5096 FHD F03
3.3K
DEVICE
UNDER
TEST
OUT
CL = 100 pF
CL INCLUDES JIG CAPACITANCE
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) Output floating (High-Z) is defined as the state where the external data line is no longer driven by the output buffer.
(3) Input Rise and Fall Times (10% to 90%) < 10 ns.
(4) Input Pulse Levels = 0.45V and 2.4V.
(5) Input and Output Timing Reference = 0.8V and 2.0V.
(6) Low-Z is defined as the state where the external data may be driven by the output buffer but may not be valid.
5108 FHD F04
5 Doc. No. 25042-00 2/98 F-1
5 Page 
Preliminary
CAT28F512
Erase-Verify Mode
The Erase-verify operation is performed on every byte
after each erase pulse to verify that the bits have been
erased.
Programming Mode
The programming operation is initiated using the pro-
gramming algorithm of Figure 7. During the first write
cycle, the command 40H is written into the command
register. During the second write cycle, the address of
the memory location to be programmed is latched on the
falling edge of WE, while the data is latched on the rising
edge of WE. The program operation terminates with the
next rising edge of WE. An integrated stop timer allows
for automatic timing control over this operation, eliminat-
ing the need for a maximum program timing specifica-
tion. Refer to AC Characteristics (Program/Erase) for
specific timing parameters.
Program-Verify Mode
A Program-verify cycle is performed to ensure that all
bits have been correctly programmed following each
byte programming operation. The specific address is
already latched from the write cycle just completed, and
stays latched until the verify is completed. The Program-
verify operation is initiated by writing C0H into the
command register. An internal reference generates the
necessary high voltages so that the user does not need
to modify VCC. Refer to AC Characteristics (Program/
Erase) for specific timing parameters.
Figure 6. A.C. Timing for Programming Operation
VCC POWER-UP SETUP PROGRAM LATCH ADDRESS
& STANDBY
COMMAND
& DATA
PROGRAM
VERIFY
PROGRAMMING COMMAND
PROGRAM VCC POWER-DOWN/
VERIFICATION
STANDBY
ADDRESSES
tWC
tWC
tAS tAH
CE (E)
tCS
tCH
tCH
tCS
tCH
OE (G)
tGHWL
tWPH
tWHWH1
tWHGL
WE (W)
DATA (I/O)
tWP
tDS
HIGH-Z
DATA IN
= 40H
tDH
tDS
tWP
DATA IN
tDH
VCC 5.0V
0V
VPP VPPH
VPPL
tVPEL
tWP
tDS
tDH
DATA IN
= C0H
tOE
tOLZ
tLZ
tCE
tRC
tEHQZ
tDF
tOH
VALID
DATA OUT
28F512 F08
11 Doc. No. 25042-00 2/98 F-1
11 Page | ||
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| PDF Descargar | [ Datasheet CAT28F512.PDF ] | |
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