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CAT28F102 fiches techniques PDF

Catalyst Semiconductor - 1 Megabit CMOS Flash Memory

Numéro de référence CAT28F102
Description 1 Megabit CMOS Flash Memory
Fabricant Catalyst Semiconductor 
Logo Catalyst Semiconductor 





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CAT28F102 fiche technique
CAT28F102
1 Megabit CMOS Flash Memory
Licensed Intel
second source
FEATURES
s Fast Read Access Time: 45/55/70/90 ns
s Low Power CMOS Dissipation:
–Active: 30 mA max (CMOS/TTL levels)
–Standby: 1 mA max (TTL levels)
–Standby: 100 µA max (CMOS levels)
s High Speed Programming:
–10 µs per byte
–1 Sec Typ Chip Program
s 0.5 Seconds Typical Chip-Erase
s 12.0V ± 5% Programming and Erase Voltage
s Commercial,Industrial and Automotive
Temperature Ranges
DESCRIPTION
The CAT28F102 is a high speed 64K x 16-bit electrically
erasable and reprogrammable Flash memory ideally
suited for applications requiring in-system or after-sale
code updates. Electrical erasure of the full memory
contents is achieved typically within 0.5 second.
It is pin and Read timing compatible with standard
EPROM and E2PROM devices. Programming and Erase
are performed through an operation and verify algo-
rithm. The instructions are input via the I/O bus, using a
BLOCK DIAGRAM
s 64K x 16 Word Organization
s Stop Timer for Program/Erase
s On-Chip Address and Data Latches
s JEDEC Standard Pinouts:
–40-pin DIP
–44-pin PLCC
–40-pin TSOP
s 100,000 Program/Erase Cycles
s 10 Year Data Retention
s Electronic Signature
two write cycle scheme. Address and Data are latched
to free the I/O bus and address bus during the write
operation.
The CAT28F102 is manufactured using Catalyst’s ad-
vanced CMOS floating gate technology. It is designed to
endure 100,000 program/erase cycles and has a data
retention of 10 years. The device is available in JEDEC
approved 40-pin DIP, 44-pin PLCC, or 40-pin TSOP
packages.
I/O0–I/O15
ERASE VOLTAGE
SWITCH
I/O BUFFERS
WE COMMAND
REGISTER
CE
OE
A0–A15
VOLTAGE VERIFY
SWITCH
© 1998 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
PROGRAM VOLTAGE
SWITCH
CE, OE LOGIC
DATA SENSE
LATCH AMP
Y-DECODER
X-DECODER
1
Y-GATING
1,048,576-BIT
MEMORY
ARRAY
28F101-1
Doc. No. 25038-0A 2/98 F-1

PagesPages 14
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