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PDF CAT28F001 Data sheet ( Hoja de datos )
| Número de pieza | CAT28F001 | |
| Descripción | 1 Megabit CMOS Boot Block Flash Memory | |
| Fabricantes | Catalyst Semiconductor | |
| Logotipo |  |
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CAT28F001
1 Megabit CMOS Boot Block Flash Memory
Licensed Intel
second source
FEATURES
s Fast Read Access Time: 70/90/120/150 ns
s On-Chip Address and Data Latches
s Blocked Architecture
— One 8 KB Boot Block w/ Lock Out
• Top or Bottom Locations
— Two 4 KB Parameter Blocks
— One 112 KB Main Block
s Low Power CMOS Operation
s 12.0V ± 5% Programming and Erase Voltage
s Automated Program & Erase Algorithms
s High Speed Programming
s Commercial, Industrial and Automotive
Temperature Ranges
s Deep Powerdown Mode
— 0.05 µA ICC Typical
— 0.8 µA IPP Typical
s Hardware Data Protection
s Electronic Signature
s 100,000 Program/Erase Cycles and 10 Year
Data Retention
s JEDEC Standard Pinouts:
— 32 pin DIP
— 32 pin PLCC
— 32 pin TSOP
s Reset/Deep Power Down Mode
DESCRIPTION
The CAT28F001 is a high speed 128K X 8 bit electrically
erasable and reprogrammable Flash memory ideally
suited for applications requiring in-system or after sale
code updates.
The CAT28F001 has a blocked architecture with one 8
KB Boot Block, two 4 KB Parameter Blocks and one 112
KB Main Block. The Boot Block section can be at the top
or bottom of the memory map and includes a reprogram-
ming write lock out feature to guarantee data integrity. It
is designed to contain secure code which will bring up
the system minimally and download code to other loca-
tions of CAT28F001.
The CAT28F001 is designed with a signature mode
which allows the user to identify the IC manufacturer and
device type. The CAT28F001 is also designed with on-
Chip Address Latches, Data Latches, Programming and
Erase Algorithms.
The CAT28F001 is manufactured using Catalyst’s ad-
vanced CMOS floating gate technology. It is designed
to endure 100,000 program/erase cycles and has a data
retention of 10 years. The device is available in JEDEC
approved 32-pin plastic DIP, PLCC or TSOP packages.
BLOCK DIAGRAM
WRITE STATE
MACHINE
RP
WE COMMAND
REGISTER
ADDRESS
COUNTER
ERASE VOLTAGE
SWITCH
PROGRAM VOLTAGE
SWITCH
CE, OE LOGIC
I/O0–I/O7
I/O BUFFERS
DATA
LATCH
STATUS
REGISTER
SENSE
AMP
CE
OE
A0–A16
VOLTAGE VERIFY
SWITCH
© 1998 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Y-DECODER
X-DECODER
1
Y-GATING
8K-BYTE BOOT BLOCK
4K-BYTE PARAMETER BLOCK
4K-BYTE PARAMETER BLOCK
112K-BYTE MAIN BLOCK
28F001 F01
Doc. No. 25071-00 2/98 F-1
1 page  
CAT28F001
SUPPLY CHARACTERISTICS
Symbol
Parameter
Limits
Min Max.
Unit
VLKO
VCC Erase/Write Lock Voltage
2.5
V
VCC VCC Supply Voltage
4.5 5.5
V
VPPL
VPP During Read Operations
0 6.5 V
VPPH
VPP During Erase/Program
11.4 12.6
V
VHH RP, OE Unlock Voltage
11.4 12.6
V
A.C. CHARACTERISTICS, Read Operation
VCC = +5V ±10%, unless otherwise specified
JEDEC Standard
Symbol Symbol
Parameter
tAVAV
tRC Read Cycle Time
28F001-70(8) 28F001-90(7)
Min. Max. Min. Max.
70 90
28F001-12(7) 28F001-15(7)
Min. Max. Min. Max. Unit
120 150
ns
tELQV
tAVQV
tGLQV
tCE CE Access Time
tACC Address Access Time
tOE OE Access Time
70 90
70 90
27 35
120 150 ns
120 150 ns
50 55 ns
-
tGLQX
tELQX
tGHQZ
tEHQZ
tOH Output Hold from Address OE/CE Change 0
0
0
0 ns
tOLZ(1)(6) OE to Output in Low-Z
0 0 0 0 ns
tLZ(1)(6)
CE to Output in Low-Z
0 0 0 0 ns
tDF(1)(2) OE High to Output High-Z
30 30 30 30 ns
tHZ(1)(2) CE High to Output High-Z
55 35 55 55 ns
tPHQV
tPWH
RP High to Output Delay
600 600 600 600 ns
Figure 1. A.C. Testing Input/Output Waveform(3)(4)(5)
2.4 V
0.45 V
INPUT PULSE LEVELS
2.0 V
0.8 V
REFERENCE POINTS
Testing Load Circuit (example)
5108 FHD F03
1.3V
Figure 2. Highspeed A.C. Testing Input/Output
Waveform(3)(4)(5)
3.0 V
0.0 V
INPUT PULSE LEVELS
1.5 V
REFERENCE POINTS
Testing Load Circuit (example)
5108 FHD F03A
1.3V
1N914
1N914
DEVICE
UNDER
TEST
3.3K
OUT
CL = 100 pF
CL INCLUDES JIG CAPACITANCE
DEVICE
UNDER
TEST
3.3K
CL = 30 pF
OUT
CL INCLUDES JIG CAPACITANCE
5108 FHD F04
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) Output floating (High-Z) is defined as the state where the external data line is no longer driven by the output buffer.
(3) Input Rise and Fall Times (10% to 90%) < 10 ns.
(4) Input Pulse Levels = 0.45V and 2.4V. For High Speed Input Pulse Levels 0.0V and 3.0V.
(5) Input and Output Timing Reference = 0.8V and 2.0V. For High Speed Input and Output Timing Reference = 1.5V.
(6) Low-Z is defined as the state where the external data may be driven by the output buffer but may not be valid.
(7) For load and reference points, see Fig. 1
(8) For load and reference points, see Fig. 2
5108 FHD F05
5 Doc. No. 25071-00 2/98 F-1
5 Page 
CAT28F001
IN-SYSTEM OPERATION
For on-board programming, the RP pin is the most
convenient means of altering the boot block. Before
issuing Program or Erase confirms commands, RP must
transition to VHH. Hold RP at this high voltage throughout
the program or erase interval (until after Status Register
confirm of successful completion). At this time, it can
return to VIH or VIL.
Figure 4 Byte Programming Flowchart
START
WRITE 40H,
BYTE ADDRESS
WRITE BYTE
ADDRESS/DATA
READ STATUS
REGISTER
SR.7 = 1?
YES
FULL STATUS
CHECK IF DESIRED
NO
BYTE PROGRAM
COMPLETED
FULL STATUS CHECK PROCEDURE
STATUS REGISTER DATA
READ (SEE ABOVE)
SR.3 = 0?
NO
VPP RANGE
ERROR
YES
SR.4 = 0?
NO BYTE PROGRAM
ERROR
YES
BYTE PROGRAM
SUCCESSFUL
Bus
Operation Command Comments
Write
Program
Setup
Data = 40H
Address = Bytes to be Programmed
Write
Program
Data to be programmed
Address = Byte to be Programmed
Read
Status Register Data.
Toggle OE or CE to update
Status Register
Check SR.7
Standby
1 = Ready, 0 = Busy
Repeat for subsequent bytes.
Full Status check can be done after each byte or after a sequence
of bytes.
Write FFH after the last byte programming operation to reset the
device to Read Array Mode.
Bus
Operation Command Comments
Standby
Check SR.3
1 = VPP Low Detect
Standby
Check SR.3
1 = Byte Program Error
SR.3 MUST be cleared, if set during a program attempt, before
further attempts are allowed by the Write State Machine.
SR.3 is only cleared by the Clear Status Register Command, in
case where multiple bytes are programmed before full status is
checked.
If error is detected, clear the Status Register before attempting retry
or other error recovery.
11 Doc. No. 25071-00 2/98 F-1
11 Page | ||
| Páginas | Total 18 Páginas | |
| PDF Descargar | [ Datasheet CAT28F001.PDF ] | |
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