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PDF CAT28C513 Data sheet ( Hoja de datos )
| Número de pieza | CAT28C513 | |
| Descripción | 512K-Bit CMOS PARALLEL E2PROM | |
| Fabricantes | Catalyst Semiconductor | |
| Logotipo |  |
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Advanced
CAT28C512/513
512K-Bit CMOS PARALLEL E2PROM
FEATURES
s Fast Read Access Times: 120/150 ns
s Low Power CMOS Dissipation:
–Active: 50 mA Max.
–Standby: 200 µA Max.
s Simple Write Operation:
–On-Chip Address and Data Latches
–Self-Timed Write Cycle with Auto-Clear
s Fast Write Cycle Time:
–5ms Max
s CMOS and TTL Compatible I/O
DESCRIPTION
The CAT28C512/513 is a fast,low power, 5V-only CMOS
parallel E2PROM organized as 64K x 8-bits. It requires
a simple interface for in-system programming. On-chip
address and data latches, self-timed write cycle with
auto-clear and VCC power up/down write protection
eliminate additional timing and protection hardware.
DATA Polling and Toggle status bits signal the start and
end of the self-timed write cycle. Additionally, the
CAT28C512/513 features hardware and software write
protection.
s Automatic Page Write Operation:
–1 to 128 Bytes in 5ms
–Page Load Timer
s End of Write Detection:
–Toggle Bit
–DATA Polling
s Hardware and Software Write Protection
s 100,000 Program/Erase Cycles
s 100 Year Data Retention
s Commercial, Industrial and Automotive
Temperature Ranges
The CAT28C512/513 is manufactured using Catalyst’s
advanced CMOS floating gate technology. It is designed
to endure 100,000 program/erase cycles and has a data
retention of 100 years. The device is available in JEDEC
approved 32-pin DIP, PLCC, 32-pin TSOP and 40-pin
TSOP packages.
BLOCK DIAGRAM
A7–A15
ADDR. BUFFER
& LATCHES
VCC
CE
OE
WE
INADVERTENT
WRITE
PROTECTION
CONTROL
A0–A6
TIMER
ADDR. BUFFER
& LATCHES
ROW
DECODER
HIGH VOLTAGE
GENERATOR
DATA POLLING
AND
TOGGLE BIT
COLUMN
DECODER
65,536 x 8
E2PROM
ARRAY
128 BYTE PAGE
REGISTER
I/O BUFFERS
I/O0–I/O7
5096 FHD F02
© 1998 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1
Doc. No. 25074-00 2/98
1 page  
Advanced
A.C. CHARACTERISTICS, Write Cycle
VCC=5V+10%, unless otherwise specified
Symbol Parameter
28C512/513-12 28C512/513-15
Min. Max. Min. Max. Units
tWC Write Cycle Time
5 5 ms
tAS Address Setup Time
0 0 ns
tAH
tCS
tCH
tCW(3)
tOES
tOEH
tWP(3)
Address Hold Time
CE Setup Time
CE Hold Time
CE Pulse Time
OE Setup Time
OE Hold Time
WE Pulse Width
50 50
00
00
100 100
00
00
100 100
ns
ns
ns
ns
ns
ns
ns
tDS Data Setup Time
50 50 ns
tDH Data Hold Time
tINIT(1) Write Inhibit Period After Power-up
tBLC(1)(4) Byte Load Cycle Time
0
5
0.1
0
10 5 10
100 0.1 100
ns
ms
µs
CAT28C512/513
Figure 1. A.C. Testing Input/Output Waveform(2)
2.4 V
0.45 V
INPUT PULSE LEVELS
2.0 V
0.8 V
REFERENCE POINTS
5096 FHD F03
Figure 2. A.C. Testing Load Circuit (example)
1.3V
1N914
DEVICE
UNDER
TEST
3.3K
OUT
CL = 100 pF
5096 FHD F04
Note:
CL INCLUDES JIG CAPACITANCE
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) Input rise and fall times (10% and 90%) < 10 ns.
(3) A write pulse of less than 20ns duration will not initiate a write cycle.
(4) A timer of duration tBLC max. begins with every LOW to HIGH transition of WE. If allowed to time out, a page or byte write will begin;
however a transition from HIGH to LOW within tBLC max. stops the timer.
5 Doc. No. 25074-00 2/98
5 Page | ||
| Páginas | Total 10 Páginas | |
| PDF Descargar | [ Datasheet CAT28C513.PDF ] | |
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