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PDF 74HC273A Data sheet ( Hoja de datos )
| Número de pieza | 74HC273A | |
| Descripción | Octal D Flip-Flop | |
| Fabricantes | ON Semiconductor | |
| Logotipo |  |
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MC74HC273A
Octal D Flip-Flop with
Common Clock and Reset
High−Performance Silicon−Gate CMOS
The MC74HC273A is identical in pinout to the LS273. The device
inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LSTTL outputs.
This device consists of eight D flip−flops with common Clock and
Reset inputs. Each flip−flop is loaded with a low−to−high transition of
the Clock input. Reset is asynchronous and active low.
Features
• Output Drive Capability: 10 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS and TTL
• Operating Voltage Range: 2.0 to 6.0 V
• Low Input Current: 1.0 mA
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance with the Requirements Defined by JEDEC Standard
No. 7 A
• Chip Complexity: 264 FETs or 66 Equivalent Gates
• NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
• These Devices are Pb−Free, Halogen Free and are RoHS Compliant
LOGIC DIAGRAM
DATA
INPUTS
D0 3
D1 4
D2 7
D3 8
D4 13
D5 14
D6 17
D7 18
CLOCK 11
2 Q0
5 Q1
6 Q2
9 Q3
12 Q4
15 Q5
16 Q6
19 Q7
NONINVERTING
OUTPUTS
RESET 1
PIN 20 = VCC
PIN 10 = GND
Design Criteria
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎInternal Gate Count*
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎInternal Gate Propagation Delay
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎInternal Gate Power Dissipation
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎSpeed Power Product
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ*Equivalent to a two−input NAND gate.
Value
66
1.5
5.0
.0075
Units
ea
ns
mW
pJ
© Semiconductor Components Industries, LLC, 2015
October, 2015 − Rev. 17
1
www.onsemi.com
SOIC−20
DW SUFFIX
CASE 751D
TSSOP−20
DT SUFFIX
CASE 948E
PIN ASSIGNMENT
RESET
Q0
D0
D1
Q1
Q2
D2
D3
Q3
GND
1
2
3
4
5
6
7
8
9
10
20 VCC
19 Q7
18 D7
17 D6
16 Q6
15 Q5
14 D5
13 D4
12 Q4
11 CLOCK
MARKING DIAGRAMS
20
20
HC273A
AWLYYWWG
HC
273A
ALYWG
G
1
SOIC−20
1
TSSOP−20
A = Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
G or G = Pb−Free Package
(Note: Microdot may be in either location)
FUNCTION TABLE
Inputs
Output
Reset Clock D
Q
L XX
L
H HH
H LL
H L X No Change
H X No Change
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
Publication Order Number:
MC74HC273A/D
1 page  
tr tf
CLOCK
Q
90%
50%
10%
tw
90%
50%
10%
1/fmax
tPLH
tPHL
tTLH tTHL
Figure 1.
MC74HC273A
SWITCHING WAVEFORMS
VCC
RESET
GND
Q
tw
50%
tPHL
50%
CLOCK
trec
50%
Figure 2.
VCC
GND
VCC
GND
DATA
CLOCK
VALID
50%
tsu th
50%
Figure 3.
VCC
GND
VCC
GND
DEVICE
UNDER
TEST
TEST POINT
OUTPUT
CL*
*Includes all probe and jig capacitance
Figure 4. Test Circuit
D0 3
D1 4
D2 7
DATA
INPUTS
D3 8
D4 13
D5 14
D6 17
D7 18
11
C
Q
DR
C
Q
DR
C
Q
DR
C
Q
DR
C
Q
DR
C
Q
DR
C
Q
DR
C
Q
DR
2 Q0
5 Q1
6 Q2
9 Q3
12 Q4
NONINVERTING
OUTPUTS
15 Q5
16 Q6
19 Q7
1
Figure 5. Expanded Logic Diagram
www.onsemi.com
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| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet 74HC273A.PDF ] | |
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