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Numéro de référence | PALCE16V8H-25 | ||
Description | EE CMOS Universal Programmable Array Logic | ||
Fabricant | Advanced Micro Devices | ||
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PALCE16V8H-15/25
EE CMOS Universal Programmable Array Logic
Advanced
Micro
Devices
DISTINCTIVE CHARACTERISTICS
• Pin, function and fuse-map compatible with all
20-pln GAL® devices
• Electrically erasable CMOS technology
provides reconfigurable logic and full
testability
• High speed CMOS technology
- 15-ns propagation delay for "-15" version
- 25-ns propagation delay for "-25" version
• Direct plug-in replacement for the PAL16R8
series and most of the PAL1OH8 series
• Outputs programmable as registered or
combinatorial in any combination
GENERAL DESCRIPTION
The PALCE16V8 is an advanced PAL® device built with
low-power, high-speed, electrically-erasable CMOS
technology. It is functionally compatible with all 20-pin
GAL devices. The macrocells provide a universal device
architecture. ThePALCE16V8 will directly replace the
PAL16R8 and PAL1OH8 series devices, with the excep-
tion of the PAL16C1.
Device logic is automatically configured according to the
user's design specification. Design is simplified by
PALASM design software, allowing automatic creation
of a programming file based on Boolean or state equa-
tions. PALASM software also verifies the design and
can provide test vectors for the finished device. Pro-
gramming can be accomplished on standard PAL
device programmers.
BLOCK DIAGRAM
• Programmable output polarity
• Programmable enable/disable control
• Preloadable output registers for testability
• Automatic register reset on power up
• Cost-effective 20-pin plastic DIP and PLCC
packages
• Programmable on standard device
programmers
• Supported by PALASM® software
• Fully tested for high programming and
functional yields and high reliability
The PALCE16V8 utilizes the familiar sum-of-products
(AND/OR) architecture that allows users to implement
complex logic functions easily and efficiently. Multiple
levels of combinatorial logic can always be reduced to
sum-of-products form, taking advantage of the very
wide input gates available in PAL devices. The equa-
tions are programmed into the device through floating-
gate cells in the AND logic array that can be erased elec-
trically.
The fixed OR array allows up to eight data product terms
per output for logic functions. The su m of these products
feeds the output macrocell. Each macrocell can be pro-
grammed as registered or combinatorial with an active-
HIGH or active-LOW output. The output configuration is
determined by two global bits and one local bit control-
ling four multiplexers in each macrocell.
PALCE16V8 Block Diagram
12015-0011<
Publication # 12015 Rev. A
Issue Date: April 1989
Amendment
iii
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Pages | Pages 30 | ||
Télécharger | [ PALCE16V8H-25 ] |
No | Description détaillée | Fabricant |
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