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PDF EL7564 Data sheet ( Hoja de datos )
| Número de pieza | EL7564 | |
| Descripción | Monolithic 4 Amp DC/DC Step-Down Regulator | |
| Fabricantes | Intersil | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de EL7564 (archivo pdf) en la parte inferior de esta página. Total 17 Páginas | ||
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NOT RECOMM®ESNEDEEDEDLFa7Ot5aR5S4NhEeWetDESIGNS
May 9, 2005
EL7564
FN7297.3
Monolithic 4 Amp DC/DC Step-Down
Regulator
The EL7564 is an integrated, full-featured synchronous step-
down regulator with output voltage adjustable from 1.0V to
3.8V. It is capable of delivering 4A continuous current at up
to 95% efficiency. The EL7564 operates at a constant
frequency pulse width modulation (PWM) mode, making
external synchronization possible. Patented on-chip
resistorless current sensing enables current mode control,
which provides cycle-by-cycle current limiting, over-current
protection, and excellent step load response. The EL7564
features power tracking, which makes the start-up
sequencing of multiple converters possible. A junction
temperature indicator conveniently monitors the silicon die
temperature, saving the designer time on the tedious
thermal characterization. The minimal external components
and full functionality make this EL7564 ideal for desktop and
portable applications.
The EL7564 is specified for operation over the -40°C to
+85°C temperature range.
Typical Application Diagrams
EL7564
[20-PIN SO (0.300”)]
TOP VIEW
C5
0.1µF
1 VREF
EN 20
C4
390pF
2 SGND
FB 19
R4 3 COSC PG 18
22Ω
C3
0.22µF
4
VDD
5 VTJ
C2
2.2nF
6 PGND
VDRV 17
VHI 16
LX 15
C6
0.22µF
L1
D1
VOUT
3.3V, 4A
VIN
5V
C1
330µF
7 PGND
LX 14
8 VIN PGND 13
4.7µH
C7
330µF
R2 C10
2.37kΩ 100pF
9 STP
10 STN
PGND 12
PGND 11
R1
1kΩ
Features
• Integrated synchronous MOSFETs and current mode
controller
• 4A continuous output current
• Up to 95% efficiency
• 4.5V to 5.5V input voltage
• Adjustable output from 1V to 3.8V
• Cycle-by-cycle current limit
• Precision reference
• ±0.5% load and line regulation
• Adjustable switching frequency to 1MHz
• Oscillator synchronization possible
• Internal soft start
• Over voltage protection
• Junction temperature indicator
• Over temperature protection
• Under voltage lockout
• Multiple supply start-up tracking
• Power good indicator
• 20-pin SO (0.300”) package
• 28-pin HTSSOP package
• Pb-Free available (RoHS compliant)
Applications
• DSP, CPU core and IO supplies
• Logic/Bus supplies
• Portable equipment
• DC/DC converter modules
• GTL + Bus power supply
Typical Application Diagrams continued on page 3
Manufactured Under U.S. Patent No. 5,7323,974
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-352-6832 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2003, 2005. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
1 page  
EL7564
Pin Descriptions
20-PIN SO
(0.300”)
1
2
3
4
5
6, 7
28-PIN
HTSSOP
1
2
3
4
5
6, 7, 8, 9
8 10, 11
9 13
10 14
11, 12, 13
15, 16
14, 15
16
18, 19, 20, 21,
22, 23
24
17 25
18 26
19 27
20 28
PIN NAME
PIN FUNCTION
VREF Bandgap reference bypass capacitor; typically 0.1µF to SGND
SGND Control circuit negative supply or signal ground
COSC Oscillator timing capacitor (see performance curves)
VDD
Control circuit positive supply; normally connected to VIN through an RC filter
VTJ Junction temperature monitor; connected with 2.2nF to 3.3nF to SGND
PGND
Ground return of the regulator; connected to the source of the low-side synchronous NMOS
power FET
VIN Power supply input of the regulator; connected to the drain of the high-side NMOS power FET
STP Auxiliary supply tracking positive input; tied to regulator output to synchronize start up with a
second supply; leave open for stand alone operation; 2µA internal pull down current
STN
Auxiliary supply tracking negative input; connect to output of a second supply to synchronize
start up; leave open for stand alone operation; 2µA internal pull up current
PGND
Ground return of the regulator; connected to the source of the low-side synchronous NMOS
power FET
LX Inductor drive pin; high current output whose average voltage equals the regulator output
voltage
VHI Positive supply of high-side driver; boot strapped from VDRV to LX with an external 0.22µF
capacitor
VDRV Positive supply of low-side driver and input voltage for high side boot strap
PG Power good window comparator output; logic 1 when regulator output is within ±10% of target
output voltage
FB Voltage feedback input; connected to external resistor divider between VOUT and SGND; a
125nA pull-up current forces VOUT to SGND in the event that FB is floating
EN Chip enable, active high; a 2µA internal pull up current enables the device if the pin is left open;
a capacitor can be added at this pin to delay the start of converter
Typical Performance Curves
VIN=5V
100
95 VO=3.3V
90
85
VO=2.8V
80
VO=1.8V
75
70
65
600 0.5 1 1.5 2 2.5 3 3.5
LOAD CURRENT IO (A)
FIGURE 1. EL7564CM EFFICIENCY
4
VIN=5V
100
95
VO=3.3V
90
85 VO=2.5V
80 VO=1.8V
75
70
65
60
0.1 0.6 1.1 1.6 2.1 2.6 3.1 3.6
IO (A)
FIGURE 2. EL7564CRE EFFICIENCY
4.1
5 FN7297.3
May 9, 2005
5 Page 
EL7564
NMOS Power FETs and Drive Circuitry
The EL7564 integrates low on-resistance (30mΩ) NMOS
FETs to achieve high efficiency at 4A. In order to use an
NMOS switch for the high-side drive it is necessary to drive
the gate voltage above the source voltage (LX). This is
accomplished by bootstrapping the VHI pin above the LX
voltage with an external capacitor CVHI and internal switch
and diode. When the low-side switch is turned on and the
LX voltage is close to GND potential, capacitor CVHI is
charged through an internal switch to VDRV, typically 5V. At
the beginning of the next cycle the high-side switch turns
on and the LX pins begin to rise from GND to VIN potential.
As the LX pin rises the positive plate of capacitor CVHI
follows and eventually reaches a value of VDRV + VIN,
typically 10V, for VDRV = VIN = 5V. This voltage is then
level shifted and used to drive the gate of the high-side
FET, via the VHI pin. A value of 0.22µF for CVHI is
recommended.
Reference
A 1.5% temperature compensated bandgap reference is
integrated in the EL7564. The external VREF capacitor acts
as the dominant pole of the amplifier and can be increased
in size to maximize transient noise rejection. A value of
0.1µF is recommended.
Oscillator
The system clock is generated by an internal relaxation
oscillator with a maximum duty-cycle of approximately 95%.
Operating frequency can be adjusted through COSC.
When external synchronization is required, always choose
COSC such that the free-running frequency is at least 20%
lower than that of the sync source to accommodate
component and temperature variations. Figure 21 shows a
typical connection.
Junction Temperature Sensor
An internal temperature sensor continuously monitors die
temperature. In the event that the die temperature exceeds
the thermal trip-point, the system is in a fault state and will
be shut down. The upper and low trip-points are set to 135°C
and 115°C respectively.
The VTJ pin is an accurate indication of the internal silicon
junction temperature (see performance curve.) The junction
temperature TJ (°C) can be determined from the following
relation:
TJ
=
75 + 1----.--2----–-----V----T----J--
0.00384
Where VTJ is the voltage at the VTJ pin in volts.
Power Good and Power On Reset
During power up the output regulator will be disabled until
VIN reaches a value of approximately 4V. About 500mV
hysteresis is present to eliminate noise-induced oscillations.
Under-voltage and over-voltage conditions on the regulator
output are detected through an internal window comparator.
A logic high on the PG output indicates that the regulated
output voltage is within about +10% of the nominal selected
EXTERNAL
OSCILLATOR
1 20
100pF BAT54S
390pF
2
3
5
19
18
16
6
EL7564
15
7 14
8 13
9 12
10 11
FIGURE 23. OSCILLATOR SYNCHRONIZATION
11 FN7297.3
May 9, 2005
11 Page | ||
| Páginas | Total 17 Páginas | |
| PDF Descargar | [ Datasheet EL7564.PDF ] | |
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