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PDF XR20M1280 Data sheet ( Hoja de datos )
| Número de pieza | XR20M1280 | |
| Descripción | I2C/SPI UART | |
| Fabricantes | Exar | |
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XR20M1280
I2C/SPI UART WITH 128-BYTE FIFO AND INTEGRATED LEVEL SHIFTERS
MAY 2011
REV. 1.0.0
GENERAL DESCRIPTION
The XR20M12801 (M1280) is a single-channel I2C/
SPI Universal Asynchronous Receiver and
Transmitter (UART) with integrated level shifters and
128 bytes of transmit and receive FIFOs.
For flexibility in a mixed voltage environment, the
M1280 has 4 VCC pins. There is a VCC pin for the
core, a VCC pin for the UART signals, a VCC pin for
the CPU interface signals and a VCC pin for the
GPIO signals. The VCC pins for the UART, GPIO
and I2C/SPI interface signals allow for the M1280 to
interface with devices operating at different voltage
levels eliminating the need for external voltage level
shifters. The VCC pin for the core voltage helps
lower the overall power consumption of applications
that use slower data rates.
The Auto RS-485 Half-Duplex Direction control
feature simplifies both the hardware and software for
half-duplex RS-485 applications. In addition, the
Multidrop mode with Auto Address detection and
Address Byte Control features increase the
performance by simplifying the software routines.
The Independent TX/RX Baud Rate Generator
feature allows the transmitter and receiver to operate
at different baud rates. In addition, the Fractional
Baud Rate Generator feature provides flexibility for
crystal/clock frequencies for generating standard and
non-standard baud rates.
The M1280 has programmable transmit and receive
FIFO trigger levels, automatic hardware and software
flow control, and data rates of up to 24 Mbps. Power
consumption of the M1280 can be minimized by
enabling the sleep mode.
The M1280 has a 16550 compatible register set that
provide users with operating status and control,
receiver error indications, and modem serial interface
controls. An internal loopback capability allows
onboard diagnostics. The M1280 has a selectable
I2C/SPI bus interface.
NOTE: 1 Covered by U.S. Patent #5,649,122.
FEATURES
• Integrated Level Shifters on CPU interface, UART
and GPIO signals
• Selectable I2C/SPI bus interface
• 26MHz maximum SPI clock
• 24Mbps maximum UART data rate
• Up to 16 GPIOs
• 128-Bytes TX and RX FIFOs
• Programmable TX/RX trigger levels
• TX/RX FIFO Level Counters
• Independent TX/RX Baud Rate Generator
• Fractional Baud Rate Generator
• Auto RTS/CTS Hardware Flow Control
• Auto XON/XOFF Software Flow Control
• Auto RS-485 Half-Duplex Direction Control
• Multidrop mode w/ Auto Address Detect (RX)
• Multidrop mode w/ Address Byte Control (TX)
• Sleep Mode with Automatic Wake-up
• Infrared (IrDA 1.0 and 1.1) mode
• 1.62V to 3.63V supply operation
• 5V tolerant inputs
• Crystal oscillator or external clock input
APPLICATIONS
• Personal Digital Assistants (PDA)
• Cellular Phones/Data Devices
• Battery-Operated Devices
• Global Positioning System (GPS)
• Bluetooth
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com
1 page  
REV. 1.0.0
Pin Description
XR20M1280
I2C/SPI UART WITH 128-BYTE FIFO AND INTEGRATED LEVEL SHIFTERS
NAME
QFN-24 QFN-32
PIN#
PIN#
QFN-40
PIN#
TYPE
DESCRIPTION
GPIO2/CD# 18 23 31 I/O General purpose I/O or UART Carrier-Detect (active low).
GPIO3/RI# 17 22 30 I/O General purpose I/O or UART Ring-Indicator (active low).
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
GPIO9
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14
GPIO15
-
-
-
-
-
-
-
-
-
-
-
-
20 24 I/O General purpose I/Os.
19 23 I/O
18 22 I/O
17 21 I/O
- 15 I/O General purpose I/Os.
- 16 I/O
- 17 I/O
- 18 I/O
- 19 I/O
- 25 I/O
- 26 I/O
- 27 I/O
ANCILLARY SIGNALS
XTAL1 22 31 39 I Crystal or external clock input. Note: This input is not 5V tolerant.
XTAL2 23 32 40 O Crystal or buffered clock output.
EN485#
11
11
12 I Enable Auto RS-485 Half-Duplex Mode. This pin is sampled upon
power-up. If this pin is HIGH, then the RTS# output can be used for
Auto RTS Hardware Flow Control or as a general purpose output. If
this pin is LOW, then the RTS# output is the Auto RS-485 Half-
Duplex direction control pin.
ENIR#
-
2
2 I Enable IR Mode. This pin is sampled upon power-up. If this pin is
HIGH, then the TX output and RX input will behave as the UART
transmit data output and UART receive data input. If this pin is
LOW, then the TX output and RX input will behave as the infrared
encoder data output and the infrared receive data input.
SLEEP/
PWRDN#
8
10 11 I/O Sleep / Power Down pin. This pin powers up as the SLEEP input.
The SLEEP input can force the UART to enter into the sleep mode
after the next byte transmitted or received without meeting any of
the sleep mode conditions.
This pin can also be configured as an output pin which can be used
to indicate to the CPU that the UART has entered the sleep mode.
This output can also be used to power down other devices.
VCC_CORE 21 30 38 Pwr 1.62V to 3.63V VCC for the core. This supply voltage is used for the
core logic including the crystal oscillator circuit.
VCC_BUS
10
13
14 Pwr 1.62V to 3.63V VCC for bus interface signals.
This supply voltage pin will determine the I/O levels of the CPU bus
interface signals.
VCC_UART 16 21 28 Pwr 1.62V to 3.63V VCC for the UART signals.
This supply voltage pin will determine the I/O levels of the UART I/O
signals including GPIO[3:0].
5
5 Page 
XR20M1280
REV. 1.0.0
I2C/SPI UART WITH 128-BYTE FIFO AND INTEGRATED LEVEL SHIFTERS
1.2 Serial Interface
The M1280 is typically used with RS-232, RS-485 and IR transceivers. The following figure shows typical
connections from the UART to the different transceivers. For more information on RS-232 and RS-485/422
transceivers, go to www.exar.com or send an e-mail to [email protected].
FIGURE 10. XR20M1280 TYPICAL SERIAL INTERFACE CONNECTIONS
VCC_UART
UART
TX
RX
DTR#
RTS#
CTS#
DSR#
CD#
R I#
GND
VCC_UART
R S -232
T ransceiver
T1 IN
R1OUT
T 2 IN
T 3 IN
R2OUT
R3OUT
R4OUT
R5OUT
GND
R S -232 Fu ll-M od em S erial Interface
VCC_UART
UART
TX
RX
RTS#
DTR#
CTS#
DSR#
CD#
RI #
VCC_UART
DI
RO
NC VCC_UART VCC_UART
NC
DE
RE#
RS-485
Transceiver
Full-duplex
TX+
TX-
RX+
RX-
GND
RS-485 Full-Duplex Serial Interface
11
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