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PDF XR88C192 Data sheet ( Hoja de datos )
| Número de pieza | XR88C192 | |
| Descripción | DUAL UNIVERSAL ASYNCHRONOUS RECEIVER AND TRANSMITTER | |
| Fabricantes | Exar | |
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XR88C92/192
DUAL UNIVERSAL ASYNCHRONOUS
RECEIVER AND TRANSMITTER
DESCRIPTION
August 2016
The XR88C92/192 is a Dual Universal Asynchronous Receiver and Transmitter with 8 (XR88C92) / 16 (XR88C192)
bytes transmit and receive FIFO. The XR88C92/192 is a pin and functional replacement for the SC26C92 and an
improved version of the Philips SCC2692 UART with faster data access and other additional features. The operating
speed of the receiver and transmitter can be selected independently from a table of eighteen fixed baud rates, a 16X
clock derived from a programmable counter/timer, or an external 1X or 16X clock. The baud rate generator and counter/
timer can operate directly from a crystal or from external clock input. The XR88C92/192 provides a power-down mode
in which the oscillator is stopped but the register contents are retained. The XR88C92/192 is fabricated in an advanced
CMOS process to achieve low power and high speed requirements.
FEATURES
Added features in devices with top marking of "D2" and
newer:
x 5 volt tolerant inputs
x Pin to pin and functional compatible to SC26C92
x Enhanced Multidrop mode operation with separate
storage for address and data tags (9th bit)
x 8 Bytes transmit/receive FIFO (XR88C92)
x16 Bytes transmit/receive FIFO (XR88C192)
x Standard baud rates from 50bps to 230.4kbps
x Non-standard baud rate of up to 1Mbps
x Transmit and Receive trigger levels
x Watch dog timer
x Programmable clock source for receiver and transmit-
ter of each channel
x Single interrupt output
x 7 Multipurpose inputs, 8 Multipurpose outputs
x 2.97 to 5.5 volt operation
x Programmable character lengths (5, 6, 7, 8)
x Parity, framing, and over run error detection
x Programmable 16-bit timer/counter
x On-chip crystal oscillator
x Power down mode
ORDERING INFORMATION
PLCC Package
Part Number
XR88C92CJ-F
XR88C92CV-F
XR88C92IJ-F
XR88C92IV-F
XR88C192CJ-F
XR88C192CV-F
XR88C192IJ-F
XR88C192IV-F
Part Number
(Tape & Reel)
XR88C92CJTR-F
XR88C92CVTR-F
XR88C92IJTR-F
XR88C92IVTR-F
XR88C192CJTR-F
XR88C192CVTR-F
XR88C192IJTR-F
XR88C192IVTR-F
Package
44-Lead PLCC
44-Lead LQFP
44-Lead PLCC
44-Lead LQFP
44-Lead PLCC
44-Lead LQFP
44-Lead PLCC
44-Lead LQFP
Operating Temperature
0° C to + 70° C
0° C to + 70° C
-40° C to + 85° C
-40° C to + 85° C
0° C to + 70° C
0° C to + 70° C
-40° C to + 85° C
-40° C to + 85° C
Note: Refer to website for most up-to-date ordering information.
Rev. 1.34
EXAR Corporation, 48720 Kato Road, Fremont, CA 94538 x (510) 668-7000 x FAX (510) 668-7017
1 page  
XR88C92/192
SYMBOL DESCRIPTION
Symbol
OP5
OP6
OP7
A0-A3
XTAL1
XTAL2
GND
-INT
IP0
IP1
IP2
Pin Signal
PLCC-44 LQFP-44 Type
Pin Description
16 9 O Multi-purpose output. General purpose output or one of the
following functions can be selected for this output pin by
programming the Output Port Confiuration Register bit 5;
-RxBRDY - Receive ready signal (Open drain output)
-RxBFULL - Receive FIFO full signal (Open drain output)
29 24 O Multi-purpose output. General purpose output or Transmit A
holding register empty interrupt (-TxARDY Open drain out-
put).
17 10 O Multi-purpose output. General purpose output or Transmit B
holding register emptyinterrupt (-TxBRDY Open drain output)
2,4, 40,42,
6,7 44,1 I Address select lines. To select internal registers.
36 30 I Crystal input 1 or external clock input. A crystal can be
connected between this pin and XTAL2 pin to utilize the
internal oscillator circuit. An external clock can be used to
clock internal circuit and baud rate generator for custom
transmission rates.
37 31 O Crystal input 2 or buffered clock output. See XTAL1.
22 16,17 Pwr Signal and power ground.
24 18 O Interrupt output (open drain, active low) This pin goes low
upon occurrence of one or more of eight maskable interrupt
conditions (when enabled by the interrupt mask register).
CPU can read the interrupt status register to determine the
interrupting condition(s). This output requires a pull-up resis-
tor.
8 2 I Multi-purpose input or Channel A Clear-To-Send (-CTSA
active low).
5 43 I Multi-purpose input or Channel B Clear-To-Send (-CTSB
active low).
40 34 I Multi-purpose input or Timer/Counter External clock input.
Rev. 1.34
5
5 Page 
XR88C92/192
framing error, and received-break conditions are the
logical OR of these respective bits, for all the data bytes
in the FIFO stack since the last reset error command
(see CRA, CRB bits 7:4) was issued. That is, beginning
immediately after the last reset-error command was
issued, a continuous logical-OR function of corre-
sponding status bits is produced in the status register as
each character enters the FIFO.
The block mode is useful in applications requiring the
exchange of blocks of information where the software
overhead of checking each character's error flags can-
not be tolerated. In this mode, entire messages can be
received and only one data integrity check is performed
at the end of each message. Although data reception in
this manner has speed advantages, there are also
disadvantages. If an error occurs within a message the
error will not be recognized until the final check is
performed. Also, there is no indication of which
character(s) is in error within the message.
Reading the status register (SRA, SRB) does not affect
the FIFO. The FIFO is “popped” only when the receive
buffer is read. If the FIFO is full when a new character is
received, that character is held in the receive shift
register until a FIFO position is available. If an additional
character is received while this state exists, the con-
tents of the FIFO are not affected, but the character
previously in the shift register is lost and the overrun-
error status bit will be set upon receipt of the start bit of
the new overrunning character.
To support flow control, a receiver can automatically
negate and reassert the request-to-send (RTS) output
(RX RTS control - see MR1A, MR1B bit-7). The request-
to-send output (at OP0 or OP1 for channel A or B
respectively) will automatically be negated by the re-
ceiver when a valid start bit is received and the FIFO
stack is full. When a FIFO position becomes available,
the request-to-send output will be reasserted automati-
cally by the receiver. Connecting the request-to-send
output to the clear-to send (CTS) input of a transmitting
device prevents overrun errors in the receiver. The RTS
output must be manually asserted the first time. There-
after, the receiver will control the RTS output.
If the FIFO stack contains characters and the receiver
is then disabled, the characters in the stack can still be
read but no additional characters can be received until
the receiver is again enabled. If the receiver is disabled
while receiving a character, or while there is a character
in the shift register waiting for a FIFO opening, these
characters are lost. If the receiver is reset, the FIFO
stack and all of the receiver status bits, the correspond-
ing output ports, and the interrupt request are reset. No
additional characters can be received until the receiver
is again enabled.
LOOPBACK MODES
Besides the normal operation mode in which the re-
ceiver and transmitter operate independently, each
XR88C92/192 channel can be configured to operate in
various looping modes (see MR2A, MR2B bits 7:6) that
are useful for local and remote system diagnostic
functions.
AUTOMATIC ECHO MODE
In this mode, the channel automatically retransmits the
received data on a bit-by-bit basis. The local CPU-to-
receiver communication continues normally but the
CPU-to-transmitter link is disabled.
LOCAL LOOPBACK MODE
In this mode, the transmitter output is internally con-
nected to the receiver input. The external TX pin is held
in the mark (high) state in this mode. By sending data
to the transmitter and checking that the data assembled
by the receiver is the same data that was sent, proper
channel operation can be assured. In this mode the
CPU-to-transmitter and CPU-to-receiver communica-
tions continue normally.
REMOTE LOOPBACK MODE
In this mode, the channel automatically retransmits the
received data on a bit-by-bit basis. The local CPU-to-
receiver and CPU-to-transmitter links are disabled. This
mode is useful in testing the receiver and transmitter
operation of a remote channel. This mode requires the
remote channel receiver to be enabled.
MULTIDROP MODE - Enhanced with Extra A/D Tag
Storage
Users can program the channel to operate in a wake-
up mode for Multidrop applications. In this mode of
operation (set MR1A, MR1B bits 4:3 = 11), the
XR88C92/192, as a master station channel connected
to several slave stations (a maximum of 256 unique
slave stations), transmits an address character fol-
lowed by a block of data characters targeted for one or
more of the slave stations. The channel receivers within
the slave stations are disabled, but they continuously
monitor the data stream sent out from the master
Rev. 1.34
11
11 Page | ||
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