PDF XR16V698 Data sheet ( Hoja de datos )

Número de pieza	XR16V698
Descripción	2.25V TO 3.6V HIGH PERFORMANCE OCTAL UART
Fabricantes	Exar
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No Preview Available ! XR16V698 2.25V TO 3.6V HIGH PERFORMANCE OCTAL UART WITH 32-BYTE FIFO JULY 2008 REV. 1.0.3 GENERAL DESCRIPTION The XR16V6981 (698), is a 2.25V to 3.6V octal Universal Asynchronous Receiver and Transmitter (UART) with 5V tolerant inputs. The highly integrated device is designed for high bandwidth requirement in communication systems. The global interrupt source register provides a complete interrupt status indication for all 8 channels to speed up interrupt parsing. Each UART has its own 16C550 compatible set of configuration registers, TX and RX FIFOs of 32 bytes, fully programmable transmit and receive FIFO trigger levels, automatic RTS/CTS or DTR/DSR hardware flow control with programmable hysteresis, automatic software (Xon/Xoff) flow control, RS-485 half-duplex direction control with programmable turn- around delay, Intel or Motorola bus interface and sleep mode with a wake-up indicator. NOTE: Covered by US patents #5,649,122 and #5,949,787 APPLICATIONS • Remote Access Servers • Ethernet Network to Serial Ports • Network Management • Factory Automation and Process Control • Point-of-Sale Systems • Multi-port RS-232/RS-422/RS-485 Cards FEATURES • 2.25V to 3.6V with 5V Tolerant Inputs • Single Interrupt output for all 8 UARTs • A Global Interrupt Source Register for all 8 UARTs • 5G “Flat” UART Registers for easier programming • Simultaneous Initialization of all UART channels • General Purpose 16-bit Timer/counter • Sleep Mode with Wake-up Indication • Highly Integrated Device for Space Saving • Each UART is independently controlled with: ■ 16C550 Compatible 5G Register Set ■ 32-byte Transmit and Receive FIFOs ■ Fractional Baud Rate Generator ■ Programmable TX and RX FIFO Trigger Level ■ Automatic RTS/CTS or DTR/DSR Flow Control ■ Automatic Xon/Xoff Software Flow Control ■ RS-485 Half-Duplex Direction Control Output with Selectable Turn-around Delay ■ Infrared (IrDA 1.0) Data Encoder/Decoder ■ Programmable Data Rate with Prescaler • Up to 15 Mbps Serial Data Rate • Pin compatible to XR16V798. Same 100-pin QFP Package (14x20x3 mm) FIGURE 1. BLOCK DIAGRAM RST# A7:A0 D7:D0 IOR# IOW# CS# INT# 16/68# Data Bus Interface Device Configuration Registers 16-bit Timer/Counter UART Channel 0 UART Regs BRG 32 Byte TX FIFO TX & RX IR ENDEC 32 Byte RX FIFO UART Channel 1 UART Channel 2 UART Channel 3 UART Channel 4 UART Channel 5 UART Channel 6 UART Channel 7 Crystal Osc/Buffer TX0, RX0, DTR0#, DSR0#, RTS0#, CTS0#, CD0#, RI0# TX7, RX7, DTR7#, DSR7#, RTS7#, CTS7#, CD7#, RI7# XTAL1 XTAL2 TMRCK Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com 1 page REV. 1.0.3 NAME TX4 RX4 RTS4# CTS4# DTR4# DSR4# CD4# RI4# TX5 RX5 RTS5# CTS5# DTR5# DSR5# CD5# RI5# TX6 RX6 RTS6# CTS6# DTR6# DSR6# CD6# RI6# TX7 PIN # 64 57 62 58 63 59 60 61 56 49 54 50 55 51 52 53 46 39 44 40 45 41 42 43 38 XR16V698 2.25V TO 3.6V HIGH PERFORMANCE OCTAL UART WITH 32-BYTE FIFO TYPE DESCRIPTION O UART channel 4 Transmit Data or infrared transmit data. I UART channel 4 Receive Data or infrared receive data. Normal RXD input idles HIGH. The infrared pulse can be inverted internally prior to decoding by setting FCTR bit-4. O UART channel 4 Request to Send or general purpose output (active LOW). See description of RTS0# pin. I UART channel 4 Clear to Send or general purpose input (active LOW). See descrip- tion of CTS0# pin. O UART channel 4 Data Terminal Ready or general purpose output (active LOW). See description of DTR0# pin. I UART channel 4 Data Set Ready or general purpose input (active LOW). See description of DSR0# pin. I UART channel 4 Carrier Detect or general purpose input (active LOW). I UART channel 4 Ring Indicator or general purpose input (active LOW). O UART channel 5 Transmit Data or infrared transmit data. I UART channel 5 Receive Data or infrared receive data. Normal RXD input idles HIGH. The infrared pulse can be inverted internally prior to decoding by setting FCTR bit-4. O UART channel 5 Request to Send or general purpose output (active LOW). See description of RTS0# pin. I UART channel 5 Clear to Send or general purpose input (active LOW). See descrip- tion of CTS0# pin. O UART channel 5 Data Terminal Ready or general purpose output (active LOW). See description of DTR0# pin. I UART channel 5 Data Set Ready or general purpose input (active LOW). See description of DSR0# pin. I UART channel 5 Carrier Detect or general purpose input (active LOW). I UART channel 5 Ring Indicator or general purpose input (active LOW). O UART channel 6 Transmit Data or infrared transmit data. I UART channel 6 Receive Data or infrared receive data. Normal RXD input idles HIGH. The infrared pulse can be inverted internally prior to decoding by setting FCTR bit-4. O UART channel 6 Request to Send or general purpose output (active LOW). See description of RTS0# pin. I UART channel 6 Clear to Send or general purpose input (active LOW). See descrip- tion of CTS0# pin. O UART channel 6 Data Terminal Ready or general purpose output (active LOW). See description of DTR0# pin. I UART channel 6 Data Set Ready or general purpose input (active LOW). See description of DSR0# pin. I UART channel 6 Carrier Detect or general purpose input (active LOW). I UART channel 6 Ring Indicator or general purpose input (active LOW). O UART channel 7 Transmit Data or infrared transmit data. 5 5 Page XR16V698 REV. 1.0.3 2.25V TO 3.6V HIGH PERFORMANCE OCTAL UART WITH 32-BYTE FIFO TABLE 4: TYPICAL DATA RATES WITH A 24 MHZ CRYSTAL OR EXTERNAL CLOCK AT 16X SAMPLING Required Output Data Rate DIVISOR FOR 16x Clock (Decimal) DIVISOR OBTAINABLE IN 698 DLM PROGRAM VALUE (HEX) DLL PROGRAM DLD PROGRAM DATA ERROR VALUE (HEX) VALUE (HEX)) RATE (%) 400000 3.75 3 12/16 0 3 C0 460800 3.2552 3 4/16 0 3 4 0.16 500000 3 3 0 3 00 750000 2 2 0 2 00 921600 1.6276 1 10/16 0 1 A 0.16 1000000 1.5 1 8/16 0 1 80 2.7 Transmitter The transmitter section comprises of an 8-bit Transmit Shift Register (TSR) and 32 bytes of FIFO which includes a byte-wide Transmit Holding Register (THR). TSR shifts out every data bit with the 16X or 8X or 4X (if 8X or 4X sampling is selected via the 8XMODE Register or 4XMODE Register) internal clock. A bit time is 16 (or 8 or 4) clock periods. The transmitter sends the start-bit followed by the number of data bits, inserts the proper parity-bit if enabled, and adds the stop-bit(s). The status of the FIFO and TSR are reported in the Line Status Register (LSR bit-5 and bit-6). 2.7.1 Transmit Holding Register (THR) - Write Only The transmit holding register is an 8-bit register providing a data interface to the host processor. The host writes transmit data byte to the THR to be converted into a serial data stream including start-bit, data bits, parity-bit and stop-bit(s). The least-significant-bit (Bit-0) becomes first data bit to go out. The THR is the input register to the transmit FIFO of 32 bytes when FIFO operation is enabled by FCR bit-0. Every time a write operation is made to the THR, the FIFO data pointer is automatically bumped to the next sequential data location. 2.7.2 Transmitter Operation in non-FIFO Mode The host loads transmit data to THR one character at a time. The THR empty flag (LSR bit-5) is set when the data byte is transferred to TSR. THR flag can generate a transmit empty interrupt (ISR bit-1) when it is enabled by IER bit-1. The TSR flag (LSR bit-6) is set when TSR becomes completely empty. FIGURE 5. TRANSMITTER OPERATION IN NON-FIFO MODE Data Byte Transmit Holding Register (THR) THR Interrupt (ISR bit-1) Enabled by IER bit-1 16X or 8X or 4X Clock Transmit Shift Register (TSR) ML SS BB TXNOFIFO1 11 11 Page

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