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PDF XRT86VL30 Data sheet ( Hoja de datos )
| Número de pieza | XRT86VL30 | |
| Descripción | T1/E1/J1 BITS ELEMENT - HARDWARE MANUAL | |
| Fabricantes | Exar | |
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XRT86VL30
T1/E1/J1 BITS ELEMENT - HARDWARE MANUAL
DECEMBER 2009
REV. 1.0.4
GENERAL DESCRIPTION
The XRT86VL30 is a single channel T1/E1/J1 BITS
clock recovery element and framer and LIU
integrated solution featuring R3 technology
(Relayless, Reconfigurable, Redundancy). The
physical interface is optimized with internal
impedance, and with the patented pad structure, the
XRT86VL30 provides protection from power failures
and hot swapping.
The XRT86VL30 contains an integrated DS1/E1/J1
framer and LIU which provides DS1/E1/J1 framing
and error accumulation in accordance with ANSI/
ITU_T specifications. The framer has its own framing
synchronizer and transmit-receive slip buffers. The
slip buffers can be independently enabled or disabled
as required and can be configured to frame to the
common DS1/E1/J1 signal formats.
The Framer block contains its own Transmit and
Receive T1/E1/J1 Framing function. There are 3
Transmit HDLC controllers which encapsulate
contents of the Transmit HDLC buffers into LAPD
Message frames. There are 3 Receive HDLC
controllers which extract the payload content of
Receive LAPD Message frames from the incoming
T1/E1/J1 data stream and write the contents into the
Receive HDLC buffers. The framer also contains a
Transmit and Overhead Data Input port, which
permits Data Link Terminal Equipment direct access
to the outbound T1/E1/J1 frames. Likewise, a
Receive Overhead output data port permits Data Link
Terminal Equipment direct access to the Data Link
bits of the inbound T1/E1/J1 frames.
The XRT86VL30 fully meets all of the latest T1/E1/J1
specifications: ANSI T1.101-1999, ANSI T1/E1.107-
1988, ANSI T1/E1.403-1995, ANSI T1/E1.231-1993,
ANSI T1/E1.408-1990, AT&T TR 62411 (12-90)
TR54016, and ITU G-703 (Including Section 13 -
Synchronization), G.704, G706 and G.733, AT&T
Pub. 43801, and ETS 300 011, 300 233, JT G.703, JT
G.704, JT G706, I.431. Extensive test and diagnostic
functions include Loop-backs, Boundary scan,
Pseudo Random bit sequence (PRBS) test pattern
generation, Performance Monitor, Bit Error Rate
(BER) meter, forced error insertion, and LAPD
unchannelized data payload processing according to
ITU-T standard Q.921.
APPLICATIONS AND FEATURES (NEXT PAGE)
FIGURE 1. XRT86VL30 SINGLE CHANNEL DS1 (T1/E1/J1) FRAMER/LIU COMBO
Local PCM
Highway
XRT86VL30
Tx Serial
Clock
Rx Serial
Clock
8kHz sync
OSC
Back Plane
1.544-16.384 Mbit/s
Tx Serial
Data In
Rx Serial
Data Out
PRBS
Generator &
Analyser
Signaling &
Alarms
System (Terminal) Side
TxON
External Data
Link Controller
Tx Overhead In
Rx Overhead Out
2-Frame
Slip Buffer
Elastic Store
Tx Framer
2-Frame
Slip Buffer
Elastic Store
Rx Framer
Performance
Monitor
HDLC/LAPD
Controllers
Tx LIU
Interface
LLB LB
Rx LIU
Interface
LIU &
Loopback
Control
TTIP
TRING
RTIP
RRING
JTAG
DMA
Interface
Microprocessor
Interface
INT
Memory
D[7:0]
3
A[11:0]
µP
Select
4 WR
ALE_AS
RD
RDY_DTACK
Intel/Motorola µP
Configuration, Control &
Status Monitor
1:2 Turns Ratio
1:1 Turns Ratio
RxLOS
Line Side
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com
1 page  
REV. 1.0.4
T1/E1/J1 BITS ELEMENT - HARDWARE MANUAL
LIST OF TABLES
XRT86VL30
Table 1:: List by Pin Number ............................................................................................................................................. 4
Table 2:: Pin Types ............................................................................................................................................................ 6
Table 3:: Pin Description Structure .................................................................................................................................... 6
Table 4:: XRT86VL30 Power Consumption .................................................................................................................... 42
Table 5:: E1 Receiver Electrical Characteristics .............................................................................................................. 50
Table 6:: T1 Receiver Electrical Characteristics .............................................................................................................. 51
Table 7:: E1 Transmitter Electrical Characteristics .......................................................................................................... 52
Table 8:: E1 Transmit Return Loss Requirement ............................................................................................................ 52
Table 9:: T1 Transmitter Electrical Characteristics .......................................................................................................... 53
Table 10:: Transmit Pulse Mask Specification ................................................................................................................. 54
Table 11:: DSX1 Interface Isolated pulse mask and corner points .................................................................................. 55
Table 12:: AC Electrical Characteristics .......................................................................................................................... 56
Table 13:: Intel Microprocessor Interface Timing Specifications ..................................................................................... 57
Table 14:: Intel Microprocessor Interface Timing Specifications ..................................................................................... 58
Table 15:: Motorola Asychronous Mode Microprocessor Interface Timing Specifications .............................................. 59
Table 16:: Power PC 403 Microprocessor Interface Timing Specifications ..................................................................... 60
II
5 Page 
REV. 1.0.4
T1/E1/J1 BITS ELEMENT - HARDWARE MANUAL
TRANSMIT SYSTEM SIDE INTERFACE
XRT86VL30
OUTPUT
SIGNAL NAME 128-PIN# 80-PIN# TYPE
DRIVE(MA)
DESCRIPTION
TxSYNC/
TxNEG
59
32 I/O
12 Transmit Single Frame Sync Pulse (TxSYNC) / Transmit
Negative Digital Input (TxNEG):
The exact function of this pin depends on the mode of opera-
tion selected, as described below.
DS1/E1 Base Rate Mode (1.544MHz/2.048MHz) - TxSYNC:
These TxSYNC pin is used to indicate the single frame
boundary within an outbound T1/E1 frame. In both DS1 or E1
mode, the single frame boundary repeats every 125 micro-
seconds (8kHz).
In DS1/E1 base rate, TxSYNC can be configured as either
input or output as described below.
When TxSYNC is configured as an Input:
Users must provide a signal which must pulse "High" for one
period of TxSERCLK during the first bit of an outbound DS1/
E1 frame. It is imperative that the TxSYNC input signal be
synchronized with the TxSERCLK input signal.
When TxSYNC is configured as an Output:
The transmit T1/E1 framer will output a signal which pulses
"High" for one period of TxSERCLK during the first bit of an
outbound DS1/E1 frame.
DS1/E1 High-Speed Backplane Modes* - TxSYNC as
INPUT ONLY:
In this mode, TxSYNC must be an input regardless of the
clock source that is chosen to be the timing source for the
transmit framer. In 2.048MVIP/4.096/8.192MHz high-speed
modes, the TxSYNC pin must be pulsed ’High’ for one period
of TxSERCLK during the first bit of the outbound T1/E1
frame. In HMVIP mode, TxSYNC0 must be pulsed ’High’ for 4
clock cycles of the TxMSYNC/TxINCLK signal in the position
of the first two and the last two bits of a multiplexed frame. In
H.100 mode, TxSYNC0 must be pulsed ’High’ for 2 clock
cycles of the TxMSYNC/TxINCLK signal in the position of the
first and the last bit of a multiplexed frame.
DS1 or E1 Framer Bypass Mode - TxNEGn
In this mode, TxSYNC is used as the negative digital input pin
(TxNEG) to the LIU.
NOTE:
*High-speed backplane modes include (For T1/E1)
2.048MVIP, 4.096MHz, 8.192MHz, 16.384MHz
HMVIP, H.100, Bit-multiplexed modes, and (For T1
only) 12.352MHz Bit-multiplexed mode.
NOTE: In DS1 high-speed modes, the DS-0 data is mapped
into an E1 frame by ignoring every fourth time slot
(don’t care).
NOTE: This pin is internally pulled “Low”.
9
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| PDF Descargar | [ Datasheet XRT86VL30.PDF ] | |
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