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PDF CLC4011 Data sheet ( Hoja de datos )
| Número de pieza | CLC4011 | |
| Descripción | Rail-to-Rail I/O Amplifiers | |
| Fabricantes | Exar | |
| Logotipo |  |
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CLC2011, CLC4011
Low Power, Low Cost, Rail-to-Rail I/O Amplifiers
General Description
The CLC2011 (dual) and CLC4011 (quad) are ultra-low cost, low power,
voltage feedback amplifiers. At 2.7V, the CLCx011 family uses only 136μA
of supply current per amplifier and are designed to operate from a supply
range of 2.5V to 5.5V (±1.25 to ±2.75). The input voltage range exceeds the
negative and positive rails.
The CLCx011 family of amplifiers offer high bipolar performance at a low
CMOS prices. They offer superior dynamic performance with 4.9MHz small
signal bandwidths and 5.3V/μs slew rates. The combination of low power,
high bandwidth, and rail-to-rail performance make the CLCx011 amplifiers
well suited for battery-powered communication/computing systems.
F E AT U R E S
■■ 136μA supply current
■■ 4.9MHz bandwidth
■■ Output swings to within 20mV of either rail
■■ Input voltage range exceeds the rail by
>250mV
■■ 5.3V/μs slew rate
■■ 21nV/√Hz input voltage noise
■■ ±35mA linear output current
■■ Fully specified at 2.7V and 5V supplies
A P P L I C AT I O N S
■■ Portable/battery-powered applications
■■ Mobile communications, cell phones,
pagers
■■ ADC buffer
■■ Active filters
■■ Portable test instruments
■■ Notebooks and PDA’s
■■ Signal conditioning
■■ Medical equipment
■■ Portable medical instrumentation
Ordering Information - back page
Large Signal Frequency Response
Vs = 5V
Vo = 1Vpp
0.01
Vo = 4Vpp
Vo = 2Vpp
0.1 1
Frequency (MHz)
10
Output Swing vs. Load
1.35
R L = 10kΩ
R L = 1kΩ
0 RL = 75Ω
R L = 100Ω
R L = 200Ω
R L = 75/100Ω
-1.35
-2.0
0
Input Voltage (0.4V/div)
2.0
© 2009 - 2014 Exar Corporation
1 / 17
exar.com/CLC2011
Rev 1D
1 page  
CLC2011 Pin Configurations
SOIC-8 / MSOP-8
OUT1 1
-IN1 2 -
+IN1 3 +
-Vs 4
8 +Vs
7 OUT2
- 6 -IN2
+ 5 +IN2
CLC2011, CLC4011
CLC2011 Pin Assignments
SOIC-8 / MSOP-8
Pin No.
1
2
3
4
5
6
7
8
Pin Name
OUT1
-IN1
+IN1
-VS
+IN2
-IN2
OUT2
+VS
Description
Output, channel 1
Negative input, channel 1
Positive input, channel 1
Negative supply
Positive input, channel 2
Negative input, channel 2
Output, channel 2
Positive supply
CLC4011 Pin Configuration
SOIC-14 / TSSOP-14
OUT1
-IN1
+IN1
+VS
+IN2
-IN2
OUT2
1
2
3
4
5
6
7
14 OUT4
13 -IN4
12 +IN4
11 -VS
10 +IN3
9 -IN3
8 OUT3
CLC4011 Pin Assignments
SOIC-14 / TSSOP-14
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Pin Name
OUT1
-IN1
+IN1
+VS
+IN2
-IN2
OUT2
OUT3
-IN3
+IN3
-VS
+IN4
-IN4
OUT4
Description
Output, channel 1
Negative input, channel 1
Positive input, channel 1
Positive supply
Positive input, channel 2
Negative input, channel 2
Output, channel 2
Output, channel 3
Negative input, channel 3
Positive input, channel 3
Negative supply
Positive input, channel 4
Negative input, channel 4
Output, channel 4
© 2009 - 2014 Exar Corporation
5 / 17
exar.com/CLC2011
Rev 1D
5 Page 
CLC2011, CLC4011
Table 1 provides the recommended RS for various capacitive
loads. The recommended RS values result in approximately
<1dB peaking in the frequency response. The Frequency
Response vs. CL plot, on page 6, illustrates the response
of the CLCx011.
CL (pF)
10pF
20pF
50pF
100pF
RS (Ω)
0
0
0
100
-3dB BW (MHz)
2.2
2.4
2.5
2
Table 1: Recommended RS vs. CL
For a given load capacitance, adjust RS to optimize the
tradeoff between settling time and bandwidth. In general,
reducing RS will increase bandwidth at the expense of
additional overshoot and ringing.
Layout Considerations
General layout and supply bypassing play major roles in
high frequency performance. Exar has evaluation boards to
use as a guide for high frequency layout and as an aid in
device testing and characterization. Follow the steps below
as a basis for high frequency layout:
■■ Include 6.8µF and 0.1µF ceramic capacitors for power supply
decoupling
■■ Place the 6.8µF capacitor within 0.75 inches of the power pin
■■ Place the 0.1µF capacitor within 0.1 inches of the power pin
■■ Remove the ground plane under and around the part,
especially near the input and output pins to reduce parasitic
capacitance
■■ Minimize all trace lengths to reduce series inductances
Refer to the evaluation board layouts below for more
information.
Evaluation Board Information
The following evaluation boards are available to aid in the
testing and layout of these devices:
Overdrive Recovery
An overdrive condition is defined as the point when either
one of the inputs or the output exceed their specified
voltage range. Overdrive recovery is the time needed for the
amplifier to return to its normal or linear operating point. The
recovery time varies, based on whether the input or output
is overdriven and by how much the range is exceeded.
The CLCx011 will typically recover in less than 50ns from
an overdrive condition. Figure 8 shows the CLC2011 in an
overdriven condition.
Evaluation Board #
CEB006
CEB010
CEB019
CEB018
Products
CLC2011 in SOIC
CLC2011 in MSOP
CLC4011 in TSSOP
CLC4011 in SOIC
Evaluation Board Schematics
Evaluation board schematics and layouts are shown in
Figures 9-16 These evaluation boards are built for dual-
supply operation. Follow these steps to use the board in a
single-supply application:
1. Short -VS to ground.
2. Use C3 and C4, if the -VS pin of the amplifier is not
directly connected to the ground plane.
Figure 8: Overdrive Recovery
© 2009 - 2014 Exar Corporation
11 / 17
exar.com/CLC2011
Rev 1D
11 Page | ||
| Páginas | Total 17 Páginas | |
| PDF Descargar | [ Datasheet CLC4011.PDF ] | |
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