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PDF ADP3167 Data sheet ( Hoja de datos )
| Número de pieza | ADP3167 | |
| Descripción | 5-Bit Programmable 2-Phase Synchronous Buck Controller | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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FEATURES
ADOPT™ Optimal Positioning Technology for Superior
Load Transient Response and Fewest Output Capacitors
Complies with VRM 9.0 with Lowest System Cost
Active Current Balancing between Both Output Phases
5-Bit Digitally Programmable 1.1 V to 1.85 V Output
Dual Logic-Level PWM Outputs for Interface to External
High Power Drivers
Total Output Accuracy ؎0.8% over Temperature
Current-Mode Operation
Short Circuit Protection
Power Good Output
Overvoltage Protection Crowbar Protects
Microprocessors with No Additional
External Components
APPLICATIONS
Desktop PC Power Supplies for:
Intel Pentium® 4 Processors
AMD Athlon™ Processors
VRM Modules
5-Bit Programmable 2-Phase
Synchronous Buck Controller
ADP3160/ADP3167
FUNCTIONAL BLOCK DIAGRAM
VCC
REF
GND
CT
COMP
UVLO
AND
BIAS
3.0V
REFERENCE
SET
RESET
CROWBAR
2-PHASE
DRIVER
LOGIC
CMP3
DAC+24%
OSCILLATOR
CMP
CMP2
DAC–18%
CMP
CMP1
ADP3160/ADP3167
VID
DAC
gm
PWM1
PWM2
PWRGD
CS–
CS+
FB
VID4 VID3 VID2 VID1 VID0
GENERAL DESCRIPTION
The ADP3160 and ADP3167 are highly efficient, dual output,
synchronous buck switching regulator controllers optimized for
converting a 5 V or 12 V main supply into the core supply voltage
required by high-performance processors, such as Pentium 4 and
Athlon. The ADP3160 uses an internal 5-bit DAC to read a volt-
age identification (VID) code directly from the processor that is
used to set the output voltage between 1.1 V and 1.85 V. The
devices use a current-mode PWM architecture to drive two logic-
level outputs at a programmable switching frequency that can be
optimized for VRM size and efficiency. The output signals are
180 degrees out of phase, allowing for the construction of two
complementary buck switching stages. These two stages share the
dc output current to reduce overall output voltage ripple. An
active current balancing function ensures that both phases carry
equal portions of the total load current, even under large transient
loads, to minimize the size of the inductors. The ADP3160 control
ADOPT is a trademark of Analog Devices, Inc.
Athlon is a trademark of Advanced Micro Devices, Inc.
Pentium is a registered trademark of Intel Corporation.
loop has been optimized for conversion from 12 V, while the
ADP3167 is designed for conversion from a 5 V supply.
The ADP3160 and ADP3167 also use a unique supplemental
regulation technique called active voltage positioning to enhance
load transient performance. Active voltage positioning results
in a dc/dc converter that meets the stringent output voltage
specifications for high-performance processors, with the minimum
number of output capacitors and smallest footprint. Unlike
voltage-mode and standard current-mode architectures, active
voltage positioning adjusts the output voltage as a function of
the load current so that it is always optimally positioned for a
system transient. They also provide accurate and reliable short
circuit protection and adjustable current limiting.
The ADP3160 is specified over the commercial temperature
range of 0∞C to 70∞C and is available in a 16-lead narrow body
SOIC package.
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2002
1 page  
5-BIT CODE
100⍀
100nF
ADP3160/ADP3167
1 VID4
2 VID3
3 VID2
4 VID1
5 VID0
6 COMP
7 FB
8 CT
VCC 16
REF 15
CS– 14
PWM1 13
PWM2 12
CS+ 11
PWRGD 10
GND 9
AD820
1.2V
20k⍀
+
1F
12V
100nF
VFB
Figure 1. Closed-Loop Output Voltage Accuracy
Test Circuit
10000
1000
100
0
100 200 300 400
CT CAPACITOR – pF
500
Figure 2. Oscillator Frequency vs. Timing Capacitor
ADP3160/ADP3167
4.10
4.05
4.00
3.95
3.90
3.85
0
250 500 750 1000 1250 1500 1750 2000
OSCILLATOR FREQUENCY – kHz
Figure 3. Supply Current vs. Oscillator Frequency
16
TA = 25؇C
VOUT = 1.6V
12
8
4
0
–1 0
OUTPUT ACCURACY – % of Nominal
1
Figure 4. Output Accuracy Distribution
REV. B
–5–
5 Page 
ADP3160/ADP3167
the data sheet for the FDB7030L, the value of QG is about 35 nC
and the peak gate drive current provided by the ADP3412 is
about 1 A. In the third term, QRR is the charge stored in the
body diode of the low-side MOSFET at the valley of the inductor
current. The data sheet of the FDB8030L does not give that
information, so an estimated value of 150 nC is used. The esti-
mate is based on information found on the data sheet of a
similar device, the IRF7809. In both terms, fSW is the actual
switching frequency of the MOSFETs, or 200 kHz. IL(PK) is the
peak current in the inductor, or 32.8 A.
Substituting the above data in Equation 19, and using the worst-
case value for the MOSFET resistance yields a conduction loss
of 0.96 W, a turn-off loss of 2.75 W, and a turn-on loss of 0.72 W.
Thus the worst-case total loss in a high-side MOSFET is 4.43 W.
The worst-case low-side MOSFET dissipation is:
PLSF = RDS(ON )LS ¥ I 2 LSF ( MAX )
PLSF = 5.6 mW ¥ (25 A)2 = 3.5 W
(19)
(Note that there are no switching losses in the low-side MOSFET.)
CIN Selection and Input Current di/dt Reduction
In continuous inductor-current mode, the source current of the
high-side MOSFET is approximately a square wave with a duty
ratio equal to VOUT/VIN and an amplitude of one-half of the
maximum output current. To prevent large voltage transients, a
low ESR input capacitor sized for the maximum rms current
must be used. The maximum rms capacitor current is given by:
IC(RMS)
=
IO
2
2 ¥ DHSF - (2 ¥ DHSF )2
(20)
IC(RMS)
=
53.4 A
2
2 ¥ 0.133 – (2 ¥ 0.133)2 = 11.9 A
Note that the capacitor manufacturer’s ripple current ratings are
often based on only 2000 hours of life. This makes it advisable
to further derate the capacitor, or to choose a capacitor rated at
a higher temperature than required. Several capacitors may be
placed in parallel to meet size or height requirements in the
design. In this example, the input capacitor bank is formed by
four 270 mF, 16 V OS-CON capacitors.
The ripple voltage across the three paralleled capacitors is:
VC(RIPPLE )
=
IO
n
¥
ÊËÁ
ESRC
nC
+
nC
DHSF
¥ CIN ¥
fSW
ˆ¯˜
(21)
VC(RIPPLE )
=
53.4
2
A
¥
ÊËÁ
18
mW
4
+
4
¥
270
0.133
mF ¥ 200
kHzˆ¯˜
=
137
mV
To reduce the input current di/dt to below the recommended
maximum of 0.1 A/ms, an additional small inductor (L > 1 mH @
15 A) should be inserted between the converter and the supply
bus. That inductor also acts as a filter between the converter and
the primary power source.
Feedback Loop Compensation Design for ADOPT
Optimized compensation of the ADP3160 and ADP3167 allow
the best possible containment of the peak-to-peak output voltage
deviation. Any practical switching power converter is inherently
limited by the inductor in its output current slew rate to a value
much less than the slew rate of the load. Therefore, any sudden
change of load current will initially flow through the output capaci-
tors, and assuming that the capacitance of the output capacitor
is larger than the critical value defined by Equation 5, this will
produce a peak output voltage deviation equal to the ESR of the
output capacitor times the load current change.
The optimal implementation of voltage positioning, ADOPT,
will create an output impedance of the power converter that is
entirely resistive over the widest possible frequency range, includ-
ing dc, and equal to the maximum acceptable ESR of the output
capacitor array. With the resistive output impedance, the output
voltage will droop in proportion with the load current at any
load current slew rate; this ensures the optimal positioning and
allows the minimization of the output capacitor.
With an ideal current-mode controlled converter, where the
average inductor current would respond without delay to the
command signal, the resistive output impedance could be
achieved by having a single-pole roll-off of the voltage gain of
the voltage-error amplifier. The pole frequency must coincide
with the ESR zero of the output capacitor. The devices use constant
frequency current-mode control, which is known to have a
nonideal, frequency dependent command signal to inductor current
transfer function. The frequency dependence manifests in the
form of a pair of complex conjugate poles at one-half of the switch-
ing frequency. A purely resistive output impedance could be
achieved by canceling the complex conjugate poles with zeros at
the same complex frequencies and adding a third pole equal to
the ESR zero of the output capacitor. Such a compensating network
would be quite complicated. Fortunately, in practice it is
sufficient to cancel the pair of complex conjugate poles with a
single real zero placed at one-half of the switching frequency.
Although the end result is not a perfectly resistive output imped-
ance, the remaining frequency dependence causes only a small
percentage of deviation from the ideal resistive response. The
single-pole and single-zero compensation can be easily implemented
by terminating the gm error amplifier with the parallel combina-
tion of a resistor and a series RC network.
The first step in the design of the feedback loop compensa-
tion is to determine the targeted output resistance, RE(MAX), of the
power converter using Equation 4. The compensation can then
be tailored to create that output impedance for the power
converter, and the quantity of output capacitors can be chosen
to create a net ESR that is less than or equal to RE(MAX).
The next step is to determine the total termination resistance of
the gm amplifier that will yield the correct output resistance:
RT
=
nI ¥ RSENSE
gm ¥ RE(MAX ) ¥ 2
RT
=
12.5 ¥ 4 mW
2.2 mmho ¥ 1.5 mW ¥ 2
=
7.57 kW
(22)
where nI is the division ratio from the output voltage signal of
the gm amplifier to the PWM comparator (CMP1), gm is the
transconductance of the gm amplifier itself, and the factor of 2 is
the result of the 2-phase configuration. Note that the internal
current multiplier (nI) is 12.5 for the ADP3160, but is 25 for
the ADP3167. For this example, assume that we use the
Rubycon capacitors at the output with their ESR of 1.44 mW.
Once RT is known, the two resistors that make up the divider
from the REF pin to output of the gm amplifier (COMP pin)
must be calculated. The resistive divider introduces an offset to
the output of the gm amplifier that, when reflected back through
the gain of the gm stage, accurately positions the output voltage
near its allowed maximum at light load. Furthermore, the output
of the gm amplifier sets the current sense threshold voltage. At no
load, the current sense threshold is increased by the peak of the
ripple current in the inductor and reduced by the delay between
REV. B
–11–
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet ADP3167.PDF ] | |
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