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PDF THC63LVD824A Data sheet ( Hoja de datos )
| Número de pieza | THC63LVD824A | |
| Descripción | LVDS Receiver | |
| Fabricantes | THine Electronics | |
| Logotipo |  |
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THC63LVD824A _Rev1.20_E
THC63LVD824A
Single(112MHz)/Dual(170MHz) Link LVDS Receiver for XGA/SXGA/SXGA+/UXGA
General Description
The THC63LVD824A receiver is designed to support
Single Link transmission between Host and Flat Panel
Display up to SXGA resolutions and Dual Link trans-
mission between Host and Flat Panel Display up to
UXGA resolutions. The THC63LVD824A converts the
LVDS data streams back into 48bits of CMOS/TTL data
with falling edge or rising edge clock for convenient
with a variety of LCD panel controllers.
In Single Link, data transmit clock frequency of
112MHz, 48bits of RGB data are transmitted at an
effective rate of 784Mbps per LVDS channel. Using a
112MHz clock, the data throughput is 392Mbytes per
second.
In Dual Link, data transmit clock frequency of 85MHz,
48bits of RGB data are transmitted at an effective rate
of 595Mbps per LVDS channel. Using a 85MHz clock,
the data throughput is 595Mbytes per second.
Features
• Wide dot clock range: 25-170MHz suited for VGA,
SVGA, XGA, SXGA, SXGA+ and UXGA
• PLL requires No external components
• Supports Single Link up to 112MHz dot clock for
SXGA
• Supports Dual Link up to 170MHz dot clock for
UXGA
• 50% output clock duty cycle
• TTL clock edge programmable
• TTL output driverbility selectable for lower EMI
• Power down mode
• Low power single 3.3V CMOS design
• 100pin TQFP
• THC63LVDF84B compatible
• Pin compatible with THC63LVD824
Block Diagram
LVDS INPUT
RA1 +/-
RB1 +/-
1st Link
RC1 +/-
RD1 +/-
RCLK1 +/-
(25 to 112MHz)
2nd Link
RA2 +/-
RB2 +/-
RC2 +/-
RD2 +/-
RCLK2 +/-
(25 to 85MHz)
R/F
/PDWN
Copyright©2014 THine Electronics, Inc.
28
PLL
28
PLL
CMOS/TTL OUTPUT
8 RED1
8
GREEN1
1st DATA
8
BLUE1
HSYNC
VSYNC
DE
RECEIVER CLOCK OUT
(12.5 to 85MHz)
8 RED2
8
GREEN2
2nd DATA
8 BLUE2
1/14 THine Electronics, Inc.
1 page  
THC63LVD824A _Rev1.20_E
Supply Current
Symbol
IRCCW
IRCCS
Parameter
Receiver Supply
Current
(Worst Case Pattern)
Receiver Power Down
Supply Current
VCC = 3.0V ~ 3.6V, Ta = -10 °C ~ +70°C
Condition(*)
Typ. Max. Units
fCLKOUT = 85MHz
MODE<1:0>=LL
CL=8pF,
Vcc=3.6V
225 mA
/PDWN = L
10 μA
Switching Characteristics
Symbol
tRCP
Parameter
Dual-in / Dual-out
CLKOUT Period
Single-in / Dual-out
tRCH CLKOUT High Time
tRCL
tRS
tRH
tTLH
tTHL
tSK
tRIP1
tRIP0
CKLOUT Low Time
TTL Data Setup to CLKOUT
TTL Data Hold from CKLOUT
TTL Low to High Transition Time
TTL High to Low Transition Time
Receiver Skew
Margin
CLKIN=85MHz
CLKIN=112MHz
Input Data Position0
Input Data Position1
tRIP6 Input Data Position2
tRIP5 Input Data Position3
tRIP4 Input Data Position4
tRIP3 Input Data Position5
tRIP2
tRPLL
tRCIP
tCK12
Input Data Position6
Phase Lock Loop Set
CLKIN Period
Skew Time between RCLK1 and
RCLK2
VCC = 3.0V ~ 3.6V, Ta = -10 °C ~ +70°C
Min.
11.76
17.85
Typ.
tRCIP
2tRCIP
Max.
Units
40.0 ns
80.0 ns
t--R----C---P- ns
2
0.3tRCP-0.5
0.3tRCP-0.5
t--R----C---P-
2
2.5
ns
ns
ns
4.0 ns
2.5 4.0 ns
-0.40
-0.25
-tSK
+0.40 ns
+0.25 ns
0.0 +tSK ns
t--R----C---I--P-
7
–
tSK
-t-R----C---I--P-
7
t--R----C---I--P-
7
+
tSK
ns
2 -t-R----C---I--P-
7
–
tSK
2 -t-R----C---I--P-
7
2 -t-R----C---I--P-
7
+
tSK
ns
3 -t-R----C---I--P-
7
–
tSK
3 -t-R----C---I--P-
7
3 -t-R----C---I--P-
7
+
tSK
ns
4 -t-R----C---I--P-
7
–
tSK
4 -t-R----C---I--P-
7
4 -t-R----C---I--P-
7
+
tSK
ns
5 -t-R----C---I--P-
7
–
tSK
5 -t-R----C---I--P-
7
5 -t-R----C---I--P-
7
+
tSK
ns
6 -t-R----C---I--P-
7
–
tSK
6 -t-R----C---I--P-
7
6 -t-R----C---I--P-
7
+
tSK
ns
10.0 ms
8.92 40.0 ns
± 0.3 t R C I P
ns
Copyright©2014 THine Electronics, Inc.
5/14 THine Electronics, Inc.
5 Page 
THC63LVD824A _Rev1.20_E
LVDS Data Inputs Timing Diagrams in Dual Link
Previous Cycle
Current Cycle
RCLK1+
RA1+/-
R16’ R15’ R14’ R13’ R12’ G12 R17 R16 R15 R14 R13 R12 G12’’
RB1+/-
G17’ G16’ G15’ G14’ G13’ B13 B12 G17 G16 G15 G14 G13 B13’’
RC1+/-
HSYNC’ B17’ B16’ B15’ B14’ DE VSYNC HSYNC B17 B16 B15 B14 DE’’
RD1+/-
B10’ G11’ G10’ R11’ R10’ x B11 B10 G11 G10 R11 R10 x’’
RCLK2+
RA2+/-
R26’ R25’ R24’ R23’ R22’ G22 R27 R26 R25 R24 R23 R22 G22’’
RB2+/-
G27’ G26’ G25’ G24’ G23’ B23 B22 G27 G26 G25 G24 G23 B23’’
RC2+/-
x’ B27’ B26’ B25’ B24’ x x x B27 B26 B25 B24 x’’
RD2+/-
B20’ G21’ G20’ R21’ R20’ x B21 B20 G21 G20 R21 R20 x’’
Copyright©2014 THine Electronics, Inc.
11/14
THine Electronics, Inc.
11 Page | ||
| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet THC63LVD824A.PDF ] | |
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