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PDF FM24V10 Data sheet ( Hoja de datos )
| Número de pieza | FM24V10 | |
| Descripción | 1-Mbit (128K x 8) Serial (I2C) F-RAM | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
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FM24V10
1-Mbit (128K × 8) Serial (I2C) F-RAM
1-Mbit (128K × 8) Serial (I2C) F-RAM
Features
■ 1-Mbit ferroelectric random access memory (F-RAM) logically
organized as 128K × 8
❐ High-endurance 100 trillion (1014) read/writes
❐ 151-year data retention (See the Data Retention and
Endurance table)
❐ NoDelay™ writes
❐ Advanced high-reliability ferroelectric process
■ Fast two-wire Serial interface (I2C)
❐ Up to 3.4-MHz frequency
❐ Direct hardware replacement for serial (I2C) EEPROM
❐ Supports legacy timings for 100 kHz and 400 kHz
■ Device ID and Serial Number
❐ Manufacturer ID and Product ID
❐ Unique Serial Number (FM24VN10)
■ Low power consumption
❐ 175 A active current at 100 kHz
❐ 90 A (typ) standby current
❐ 5 A (typ) sleep mode current
■ Low-voltage operation: VDD = 2.0 V to 3.6 V
■ Industrial temperature: –40 C to +85 C
■ 8-pin small outline integrated circuit (SOIC) package
■ Restriction of hazardous substances (RoHS) compliant
Functional Description
The FM24V10 is a 1-Mbit nonvolatile memory employing an
advanced ferroelectric process. A ferroelectric random access
memory or F-RAM is nonvolatile and performs reads and writes
similar to a RAM. It provides reliable data retention for 151 years
while eliminating the complexities, overhead, and system-level
reliability problems caused by EEPROM and other nonvolatile
memories.
Unlike EEPROM, the FM24V10 performs write operations at bus
speed. No write delays are incurred. Data is written to the
memory array immediately after each byte is successfully
transferred to the device. The next bus cycle can commence
without the need for data polling. In addition, the product offers
substantial write endurance compared with other nonvolatile
memories. Also, F-RAM exhibits much lower power during writes
than EEPROM since write operations do not require an internally
elevated power supply voltage for write circuits. The FM24V10 is
capable of supporting 1014 read/write cycles, or 100 million times
more write cycles than EEPROM.
These capabilities make the FM24V10 ideal for nonvolatile
memory applications, requiring frequent or rapid writes.
Examples range from data logging, where the number of write
cycles may be critical, to demanding industrial controls where the
long write time of EEPROM can cause data loss. The
combination of features allows more frequent data writing with
less overhead for the system.
The FM24V10 provides substantial benefits to users of serial
(I2C) EEPROM as a hardware drop-in replacement. The
FM24VN10 is offered with a unique serial number that is
read-only and can be used to identify a board or system. Both
devices incorporate a read-only Device ID that allows the host to
determine the manufacturer, product density, and product
revision. The device specifications are guaranteed over an
industrial temperature range of –40 C to +85 C.
For a complete list of related documentation, click here.
Logic Block Diagram
Counter
Address
Latch
17
128 K x 8
F-RAM Array
SDA
SCL
WP
A2-A1
Serial to Parallel
Converter
Control Logic
8
8
Data Latch
8
Device ID and
Serial Number
Errata: STOP condition is optional for sleep mode entry. For more information, see Errata on page 19. Details include errata trigger conditions, scope of impact, available
workarounds, and silicon revision applicability.
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-84463 Rev. *H
• San Jose, CA 95134-1709 • 408-943-2600
Revised July 22, 2016
1 page  
FM24V10
full pagewidth
SDA
Figure 3. START and STOP Conditions
SDA
SCL
S
START Condition
P
STOP Condition
SCL
handbook, full pagewidth
SDA
MSB
Figure 4. Data Transfer on the I2C Bus
Acknowledgement
signal from slave
P
Acknowledgement S
signal from receiver
SCL
S
1
START
condition
2
789
ACK
Byte complete
1
2 3 4-8
9
ACK
S
or
P
STOP or
START
condition
Data/Address Transfer
All data transfers (including addresses) take place while the SCL
signal is HIGH. Except under the three conditions described
above, the SDA signal should not change while SCL is HIGH.
Acknowledge / No-acknowledge
The acknowledge takes place after the 8th data bit has been
transferred in any transaction. During this state the transmitter
should release the SDA bus to allow the receiver to drive it. The
receiver drives the SDA signal LOW to acknowledge receipt of
the byte. If the receiver does not drive SDA LOW, the condition
is a no-acknowledge and the operation is aborted.
The receiver would fail to acknowledge for two distinct reasons.
First is that a byte transfer fails. In this case, the no-acknowledge
ceases the current operation so that the device can be
addressed again. This allows the last byte to be recovered in the
event of a communication error.
Second and most common, the receiver does not acknowledge
to deliberately end an operation. For example, during a read
operation, the FM24V10 will continue to place data onto the bus
as long as the receiver sends acknowledges (and clocks). When
a read operation is complete and no more data is needed, the
receiver must not acknowledge the last byte. If the receiver
acknowledges the last byte, this will cause the FM24V10 to
attempt to drive the bus on the next clock while the master is
sending a new command such as STOP.
Figure 5. Acknowledge on the I2C Bus
handbook, full pagewidth
DATA OUTPUT
BY MASTER
DATA OUTPUT
BY SLAVE
No Acknowledge
Acknowledge
SCL FROM
MASTER
S
START
Condition
1
2
89
Clock pulse for
acknowledgement
Document Number: 001-84463 Rev. *H
Page 5 of 22
5 Page 
Function to Calculate CRC
BYTE calcCRC8( BYTE* pData, int nBytes )
{
static BYTE crctable[256] = {
0x00, 0x07, 0x0E, 0x09, 0x1C, 0x1B, 0x12, 0x15,
0x38, 0x3F, 0x36, 0x31, 0x24, 0x23, 0x2A, 0x2D,
0x70, 0x77, 0x7E, 0x79, 0x6C, 0x6B, 0x62, 0x65,
0x48, 0x4F, 0x46, 0x41, 0x54, 0x53, 0x5A, 0x5D,
0xE0, 0xE7, 0xEE, 0xE9, 0xFC, 0xFB, 0xF2, 0xF5,
0xD8, 0xDF, 0xD6, 0xD1, 0xC4, 0xC3, 0xCA, 0xCD,
0x90, 0x97, 0x9E, 0x99, 0x8C, 0x8B, 0x82, 0x85,
0xA8, 0xAF, 0xA6, 0xA1, 0xB4, 0xB3, 0xBA, 0xBD,
0xC7, 0xC0, 0xC9, 0xCE, 0xDB, 0xDC, 0xD5, 0xD2,
0xFF, 0xF8, 0xF1, 0xF6, 0xE3, 0xE4, 0xED, 0xEA,
0xB7, 0xB0, 0xB9, 0xBE, 0xAB, 0xAC, 0xA5, 0xA2,
0x8F, 0x88, 0x81, 0x86, 0x93, 0x94, 0x9D, 0x9A,
0x27, 0x20, 0x29, 0x2E, 0x3B, 0x3C, 0x35, 0x32,
0x1F, 0x18, 0x11, 0x16, 0x03, 0x04, 0x0D, 0x0A,
0x57, 0x50, 0x59, 0x5E, 0x4B, 0x4C, 0x45, 0x42,
0x6F, 0x68, 0x61, 0x66, 0x73, 0x74, 0x7D, 0x7A,
0x89, 0x8E, 0x87, 0x80, 0x95, 0x92, 0x9B, 0x9C,
0xB1, 0xB6, 0xBF, 0xB8, 0xAD, 0xAA, 0xA3, 0xA4,
0xF9, 0xFE, 0xF7, 0xF0, 0xE5, 0xE2, 0xEB, 0xEC,
0xC1, 0xC6, 0xCF, 0xC8, 0xDD, 0xDA, 0xD3, 0xD4,
0x69, 0x6E, 0x67, 0x60, 0x75, 0x72, 0x7B, 0x7C,
0x51, 0x56, 0x5F, 0x58, 0x4D, 0x4A, 0x43, 0x44,
0x19, 0x1E, 0x17, 0x10, 0x05, 0x02, 0x0B, 0x0C,
0x21, 0x26, 0x2F, 0x28, 0x3D, 0x3A, 0x33, 0x34,
0x4E, 0x49, 0x40, 0x47, 0x52, 0x55, 0x5C, 0x5B,
0x76, 0x71, 0x78, 0x7F, 0x6A, 0x6D, 0x64, 0x63,
0x3E, 0x39, 0x30, 0x37, 0x22, 0x25, 0x2C, 0x2B,
0x06, 0x01, 0x08, 0x0F, 0x1A, 0x1D, 0x14, 0x13,
0xAE, 0xA9, 0xA0, 0xA7, 0xB2, 0xB5, 0xBC, 0xBB,
0x96, 0x91, 0x98, 0x9F, 0x8A, 0x8D, 0x84, 0x83,
0xDE, 0xD9, 0xD0, 0xD7, 0xC2, 0xC5, 0xCC, 0xCB,
0xE6, 0xE1, 0xE8, 0xEF, 0xFA, 0xFD, 0xF4, 0xF3
};
BYTE crc = 0;
.................... while( nBytes-- ) crc = crctable[crc ^ *pData++];
return crc;
}
Document Number: 001-84463 Rev. *H
FM24V10
Page 11 of 22
11 Page | ||
| Páginas | Total 22 Páginas | |
| PDF Descargar | [ Datasheet FM24V10.PDF ] | |
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